ShareCG: Power, accuracy and noise aspects in CMOS mixed-signal



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This chapter surveys the content of the thesis. In section 8.1 a summary of the contents is given, while section 8.2 presents the main conclusions. Original contributions of this work are discussed in section 8.3 and recommendations for further research will follow in section 8.4.

    8.1. Summary

    The work presented in this thesis concerns power, noise and accuracy in mixed-signal applications. Along the material presented it is shown that power, noise and accuracy should be treated in an unitary way, the three terms being well inter-related. It is divided in a theoretical part which covers sub-micron digital and sub-micron analog and an applicative part where accuracy related power and noise related power is encountered.

    The main part of the thesis deals with analog circuits working in a digital environment where the process has been optimized for digital applications. To get the best performance, knowing the limits of power in digital and clearly defining the environment where analog should work is a must. Starting from fundamental/physical limits we are discussing afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis with analog solutions. A simple example of a digital filter shows how power can be saved at the architecture level. The possible ways to low-power in digital are being discussed which provide some input for the analog part of this thesis.

    The general trend, in digital, to scale down the power supply makes the process of designing analog circuits a difficult task since most of the solutions valid for large supply voltages are not anymore useful due to the low voltage limitations. In all cases this yields an increase in power consumption. Besides, analog designers have to cope with second order effects generated by the incompatibility of the process with analog performance. Starting from general considerations and simple circuits, we have proven that DR*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode. Matching imposes also restrictions on the obtainable accuracy and that is why, accuracy related power consumption has been discussed. The theoretical background from Chapter 2 and Chapter 3 has be used in the applications part. Several examples have been chosen where accuracy driven power and noise driven power applies.

    At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction. For this reason, a key target is to keep the largest possible voltage swing. The first example is an OTA-C integrator with a high DR/P ratio. This is possible by keeping large swing for all tuning conditions. The second example is a current Gm-C integrator with high quality factor for low voltages. The power efficiency of the two designs has been discussed according to the theoretical background from Chapter 3. The two integrators presented above are used to realize the video filter from Chapter2 in an analog way and to make a comparison in power to the digital approach. The next example is a polyphase filter. Here selectivity is ensured by using polyphase signals instead of high-Q bandpass filters. Matching driven power consumption comes as a variable. By using the current Gm-C integrator, we have shown how to make a low power polyphase filter needed for image rejection in a mobile transceiver.

    The next chapter considers the 1/f noise and offset in mixed-signal design where chopping can provide a solution to boost the dynamic range and accuracy. A method to use chopper modulation at high frequencies is introduced and a low-voltage, low-power, chopped transconductance amplifier for mixed analogue digital applications has been presented. This OTA is meant for high-end audio applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. We show next that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the reference. The same chopped OTA for high-end audio applications has a power consumption of 600mW while in the bandgap example the power consumption is 7.5 mW. This example explains why the term "low power" has to be related to the specific application and its own specs.

    The next chapter focuses on the design and the realization of low voltage chopped amplifiers with rail to rail class AB output stages capable of chopping up to 10MHZ, with low noise, high linearity and low residual offset. This amplifiers can be used for high-end audio applications in driving low-ohmic loads for portable applications. Low-power techniques at the highest level of abstraction as architectural level and algorithmic level can lead to power savings which cannot be obtained unless the complete system is taken into study.

    Chapter 7 presents a 16-bit D/A interface with Sinc approximation in the time-domain or frequency domain reconstruction filter as an example of a system where accuracy and noise give constraints on the power consumption of the system. Here, reducing power in the analog domain the power in the digital domain is also reduced while the best partitioning of the system in terms of power can be found. Compared to the standard solutions we have reduced about four times the number of coefficients of the FIR filter for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of out of band noise. A differential solution was proposed to reduce the digital crosstalk and to increase the output signal swing. An analysis of the matching, noise and clock jitter has been attached.

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