Power considerations in sub-micron digital CMOS
This chapter deals with power considerations in submicron analog CMOS. The context in which analog functionality has to be integrated is a submicron, digital process optimized for digital applications. The consequences on analog requirements have been discussed. The roadmap for scaled down processes for digital applications point to lower and lower supply voltages. For analog functions, the reduction of supply voltages has a negative influence on dynamic range and power dissipation. It is shown that low voltage is incompatible with low power when analog signal processing circuits are being considered.
The fundamental limits for low-power in analog are asymptotic limits. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. That is why relative comparisons between different designs are difficult to be made based only on the fundamental limits. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Low voltage and low power are imposed by the application and the mixed level context. It would be useful to know practical limits of power in order to make choices between different possible solutions considering the active power, voltage supply, circuit topology, noise and linearity.
Starting from general considerations and simple circuits, it is possible to prove that DR*Speed product is limited by power, topology and supply voltage regardless if the circuits are continuous time or sampled data, current-mode or voltage mode. Most of those circuits are extensively used in the designs presented in Chapter 4, Chapter 5, Chapter 6 and Chapter 7. Only white noise is taken into considerations. We have shown that scaling down VDD and keeping the same DR*GBW product, power has to increase faster in voltage-mode circuits to compensate for power supply down-scaling.
The accuracy requirements give extra boundaries on the minimal power consumption for a given speed, gain and accuracy. This limitation is stronger than the physical limitation imposed by the effect of the thermal noise given the levels of the noise and the levels of the offsets. That is why matching driven power consumption has been considered. By scaling down VDD and keeping the same G GBW A2CC,rel product, power has to increase faster in voltage-mode circuits to compensate for power supply down-scaling. The same result has been obtained from the noise driven power consumption analysis.