Power considerations in sub-micron digital CMOS
Low-power design methods can be considered at several abstraction levels as system, algorithmic, architectural, logical and physical. Low-power techniques at the highest level of abstraction as algorithmic and architectural can lead to power savings of several orders of magnitude. At this level of abstraction, power analysis allows an early prediction and optimization of the power of a system. Starting from fundamental/physical limits we are discussing afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis with analog solutions.
In section 2.3 the relationship between power consumption and S/N has been discussed. The assumption made is that quantization noise comes from only one noise source. In practical situations this is however not true. When processing with a fixed number of bits, quantization will occur to prevent the increase of number of bits after multiplication. A more accurate approach is presented in section 2.4.
Because the computational power of an algorithm implemented in a one chip solution dominates over other sources of power consumption, we have considered only the computational power. Every multiplication can be replaced by shift and add operations. That is why, the adders are the most important building blocks used in DSP’s and microprocessors. The adder cell is an elementary unit in multipliers and dividers. The aim of section 2.5 is to provide a methodology to find the computational power by starting from the type of adder. Composing other functions at a higher level, multiplier-like, is possible by using the results of this section.
Although the main part of this thesis focuses more on power related to analog circuits, the working environment for analog circuits treated here is a mixed level environment. Therefore, ways to low-power in digital and their influence on analog functionality are being discussed. They will provide some input for the analog part of this thesis.
In the last section a simple example of a digital filter shows how power can be saved at the architecture level by using CSD formats for filter coefficients. Multiplication here will be replaced with shift and add operation eliminating thus an expensive and power consumptive building block. The same filter will be realized in an analog in Chapter 4 and the results compared to digital implementation.