Logic Design for ArrayBased Circuitsby Donnamaie E. WhiteCopyright © 1996, 2001, 2002 Donnamaie E. White 


External SetUp and Hold TimesLast Edit July 22, 2001 IntroductionWhen the input to the data (D) or the clock (C) or both pins on a flip/flop or a latch are supplied from an external signal, then the external setup and hold times must be computed. The computations must be for the worstcase and account for processing skew. The worstcase may be the worstcase maximum conditions or the worstcase minimum conditions. Hold time violations are a concern wherever two storage elements interface with each other and are clocked by different drivers. An example structure is parallelclocked register flip/flops driven by multiple clock macros. Any multiple clock organization or clock distribution tree is subject to this design hazard. The error occurs when the Q output of one flip/flop (or latch) directly feeds the D input of another. If the clock to the second flip/flop is delayed due to tracking or skew, the D input may change during the setup/hold window. This can be avoided by using the guidelines and design checks described in this chapter. (See the Case Study: Preventing Hold Violations Due to Clock Skew.) To meet design submission requirements, both the maximum worstcase and the minimum worstcase equations need to be computed to determine the worstcase window for external setup and hold times for the specified operating conditions. Both rising edge and falling edge input path propagation must be evaluated. For deeplynested paths, consult the array vendor for other effects that must be considered. Figure 61 illustrates the delay paths. The data delay path is T_{D}; the clock delay path is T_{C}. Depending on the methods used to specify macro timing, the data and clock paths may need to be divided into interface and internal macro components. Results computed or derived from simulations using FrontAnnotation data cannot be considered as the circuit specification. Those derived from BackAnnotation are considered to be the specification. Figure 61 External SetUp And Hold  Clock And Data Paths There may be no internal macros in the data or the clock path or both, leaving the interface macro and the extrinsic loading as the only components in the paths. There may be multiple internal macros in a clock buffer tree while the data path is unloaded, or the data path may be heavily loaded while the clock path remains relatively simple. The relative loading between these two paths will determine whether the setup or hold time is negative or positive and how large the setup and hold window will be. The intrinsic setup and hold time of the latch or flip/flop is another factor in the equation. Figure 62 External SetUp And Hold Times  Interpretation Figure 62 diagrams the definitions of positive setup and hold times. Data must be held stable relative to the associated clock during these times. The time span indicated by the setup and hold times is referred to as a timing "window". The term window is used since the external setup and hold computations will produce a wider timing range than will be exhibited by any single die. For one set of operating conditions, the setup time is computed assuming that the data path is worstcase maximum and the clock is worstcase minimum. The hold time reverses this and is computed assuming that the clock path is worstcase maximum and the data path is worstcase minimum. The resulting range is designed to encompass all extremes of voltage, temperature and process. (See Figure 63.) Figure 63 WorstCase Range Figure 63 diagrams the worstcase window produced from the maximum external setup time and the maximum external hold time. The conditions under which these two values are computed are inconsistent and contradictory with each other, thereby ensuring that the setup and hold timing "window" for the same two signals for any single array is contained within the computed range. . 
Copyright @ 2001,
2002 Donnamaie E. White, White
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