Logic Design for ArrayBased Circuitsby Donnamaie E. WhiteCopyright © 1996, 2001, 2002 Donnamaie E. White 


Timing Analysis for ArraysLast Edit July 22, 2001 Computing L_{fo}Compute L_{fo} by adding the sum of the electrical loads of all loads driven. If a destination pin has a fanin of 2, it counts as two electrical loads and as one physical pin. A destination may appear to have two physical loads internal to the macro. In these cases, the macro documentation will clearly identify the fanin load represented by that pin. BiCMOS libraries have a higher average fanin than do bipolar libraries. Computing L_{wo}Compute L_{wo} by multiplying the wireOR load factor by the size of the wireOR. For libraries that do not allow a wireOR, this term becomes zero. Example: For the AMCC Q5000, WIREOR4 = 1.2 loads. Computing L_{net}For a nonRC tree, nondistributed estimate of metal delays, use the vendorsupplied equation to find the metal loading. The cell sizes on the larger arrays in the same family are the same as for the smaller arrays. Since the distance from edge to edge of the array is larger, the average distance for an interconnect is larger. Therefore, the same macro path would be estimated as longer on the larger array than on the smaller one. Note that this is strictly the estimate  the actual delay will depend upon the macro positions and the actual routing paths. ExampleAMCC uses:
where (net size  1) is the physical pin count of the loads driven plus the number of sources on the net (assuming a wireOR) minus one. When there is no wireOR, (net size  1) reduces to pins driven. Q2000 Series a and b factors (Historical) For the Q5000, b = 0.67 and a varies by array. The Q5000T uses a = 3.84 and the Q1300T uses a = 1.96. For a macro driving a net sized 8 (net size  1 = 7), this converts to 14.14 load units for the Q5000T and 6.63 load units for the Q1300T. Exercises


Copyright @ 2001,
2002 Donnamaie E. White, White
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