In Figure 7.3, we see a Hard IP reuse flow. It is a very simple flow. Minor adjustments may or may not be needed. The same is true for the setup step. As we discussed in Chapter %, if we want to maintain certain levels of layout hierarchy, the layout needs to be cut into smaller pieces such as memory cells, multiplier cells, barrel shifters, etc. Finally, the pieces could be major blocks of a chip like CPUs, complete RAMs, etc. Cut lines defining the boundaries of these cells or blocks can be determined by a compactor automatically or with manual assistance. Often, manual assistance has positive effects on the compacted results. The feedback loop could also be used for optimization, but other pieces of software, such as EDA analysis tools, arc then often needed to automate and analyze some of the optimization steps.
Figure 7.3 Simple Hard IP Flow
We will now look at the essential steps in the design flows and comment later on some of the additional challenges that are on the horizon. Rather than to show recursive steps in the flow diagram, we will discuss their possibilities in the text.
The main focus in this and the following sections is to try to identify measures of comparison between the efforts to get a workable chip using any of these three approaches. For these reasons, we will limit the observations to steps in the flows that are critical for comparing the flows with respect to the major challenges in bringing a chip to the market.
While it is difficult to decide, a priori, where it "will hurt the most" for the large range of requirements, we do have a pretty good general idea of the main challenges VLSI chips face. For most of them, it is time-to-market; for some, it may be economics. Then again, for some special requirements, it could simply be the maximum performance one can squeeze out of a chip. For others, such as for applications in space, the goal might be to maximize reliability. Finally, the choice of flow could be made based on a shortage of highly skilled engineers required to design a totally new chip. The priorities may be many.
Because of this multitude of potential priorities, we will focus primarily below on the strengths of the three flows suggested above in stressing IP reuse as opposed to starting from scratch every time we need a higher performance chip.
We have seen design flows for pre-DSM and DSM technologies. The main difference between the two is that, for DSM technologies, we try to shift timing analysis to the end once the physical layout is complete or almost complete. For pre-DSM, we can determine accurate timing as soon as we have selected the active components for the circuit. Clearly, for any design, the sooner we have reliable timing information, the better. When using compaction as a postlayout step, timing data that is not "too far off is good enough to achieve timing closure.