The concept of Hard IP reuse through retargeting has been discussed in Chapter 2. IP reuse, part of which is Hard IP reuse, has been the first approach believed to solve the design productivity crisis and it has been quietly practiced for many years by using a linear shrink. For DSM VLSI chips, however, linear shrink is inadequate and needs to be replaced by compaction, since compaction takes full advantage of the changes possible in layout geometries. Compaction became popular when the desire to create process-portable designs emerged and was first used on a large scale in silicon compilation.
In the late 70s and early 80s, silicon compilation was pioneered by Carver Mead and Dave Johannsen at CalTech. Silicon compilation then became the core of technologies for start-ups like Silicon Compilers in the Silicon Valley and Sagantec in the Netherlands. When silicon compilation, did not “take off” as expected, Sagantec decided to use the compaction technology inside their silicon compiler engine to attack Hard IP retargeting long before anybody in engineering knew that IP could mean anything more than a networking term.
Through much research and a lot of experience with migrating first libraries, a product called “DREAM”, an acronym for Design Rule Enforcement And Migration, was created. DREAM is today the most widely used tool for Hard IP retargeting and very robust. DREAM has been steadily expanding, thanks to the steadily increasing complexity of processing rules and feedback from customers worldwide. DREAM is now a solid product capable of retargeting designs as simple as libraries and as complex as chips in the one to two million transistors range. Since the description of Hard IP retargeting in Chapter 2 was based on DREAM, the description given there basically reflects its functional capabilities. We will not use any more space talking about the various features of DREAM here.
As is well known when talking about software, well established products, while very robust, ultimately can be surpassed with newer, previously unknown algorithms. Sagantec recently introduced a new product, called Hurricane, a vintage 2000 product that is based on a completely newly designed compaction engine, with features paralleling DREAM but running much faster and handling much larger capacity layouts. As is generally known, software speeds often follow a linear curve with capacity until they “hit” that famous breakpoint (knee) where the relationships between speed and capacity become nonlinear and the process slows down. That breakpoint (knee) has been extended by orders of magnitude compared with DREAM for Hurricane. Thus, increasingly, DREAM will be used for library migrations while Hurricane will be used for the migration of large Hard IP blocks and ICs.
We have already talked about the setup phase for migration jobs. When interacting with a terminal, some engineers like to type. However, engineers who arc especially conceptually and visually minded generally love a nice graphical user interface (GUI). A nice GUI called EnCORe (Environment for Core Optimization and Reuse) has recently been introduced. EnCORe makes it easier for designers of all skill levels to set up technology and design migration parameters. With EnCORe, all Sagantec products utilize a common process database that serves as a central repository accessible through templates containing all the basic data belonging to certain foundries. It makes the process of adjusting certain process parameters “on the fly” particularly easy.
Today's most sophisticated DSM VLSI chips consist of a lot of polygons. For most steps in the design of complex chips, the best strategy is to slay as far away as possible from the low-level details of the physical implementation of the desired functions. Thus, when designing complex VLSI chips, design work will be organized whenever possible in a modular fashion and based on a high-level functional or behavioral approach.
For the modular approach, large designs will be divided into major functional blocks. This approach, referred to as “divide and conquer ” has advantages like dealing with smaller blocks, letting each block be designed by a specialist for the particular function, and many other advantages. Each block in itself may have additional hierarchical levels. Most designers want to maintain the original identity/modularity and hierarchy of these blocks through migration.
For many years, it was impossible to migrate fully hierarchically. Now, a fully hierarchical retargeting tool is available on the market. It is a tool from Sagantec named SiClone. Though simple, one example of the migration of a layout will demonstrate one aspect of full hierarchy maintenance.
In Chapter 2, we discussed how we can maintain the hierarchy for a traditional compaction engine such as DREAM, and therefore the identity of cells in a regular array such as a memory array. To achieve this result, the user has to identify cut lines or let the compactor do it automatically for him or her. Then the array is migrated by migrating a single cell with the subsequent tiling of the array coming together like Lego blocks.
User input is not required to define hierarchy for a compaction engine that maintains all levels of a hierarchy. In this simple example, this means no cut lines need to be defined, the array will be migrated as a whole, and yet all cells have the original hierarchy and are clearly identifiable in the migrated array. While it is difficult to show the complete hierarchy maintenance in a picture of such a migrated array, the identity of the cells is clearly visible as shown in Figure 6.1 of a hierarchically migrated memory array, migrated with SiClone.
Fig. 6.1 A Memory Array Migrated While Maintaining Hierarchy
With traditional compaction, a flat migration is sometimes performed because the user does not want to bother with the required setup or because he or she does not know how. With SiClone, this setup is no longer needed, saving time. For layouts with overlaps, it is not possible to introduce cut lines. SiClone allows hierarchical maintenance for layouts with overlaps, as well.