To find accurate values for the capacitive components as shown in Figure 3.4, complex boundary value problems in conjunction with second order partial differential equations, such a Poisson's or Laplace's equation, and integral equations, such as Gauss's Law, need to be solved. For all but the simplest geometries, there are no closed form solutions for these equations. In other words, there are no exact solutions that would yield a neat analytical, completely accurate expression resulting in nice curves that express the needed capacitance values as a function of any range of the geometrical dimensions, such as the width, separation from the substrate, distance from nearest neighbor connectors and other significant parameters.
A quick review of any book on field theory, such as , in conjunction with a book containing a section on boundary value problems  will show interested readers the following:
It is obvious that the finer the mesh for determining partial capacitances, the larger the investment in computer power and the more accurate the results. Also, the more contorted the electrical field lines are, the finer the mesh has to be. For every pair of poles, all the partial capacitances add up to the total capacitance. If there are several pairs of poles, the capacitances for each one of them has to be determined. The total capacitance from all pairs of poles is the superposition of all capacitances. This is a big but unavoidable job for current DSM VLSI chips.
As we can see in Figure 3.5, once the electrical field configurations and the partial capacitances have been calculated and summed up, curves result as shown in Figure 3.5. They give us the values for many of the capacitances we might have to know. That's the good news. The bad news is that the curves in Figure 3.5 are only a function of the spacing between interconnects. This means that more work is required. Eventually, we need curves for all the relevant capacitances as a function of all the significant geometrical variables. Then, once we have all of these curves, we have to find an analytical expression that describes these curves. This is a curve-fitting process. Design tools can work with analytical expressions that are based on such curves.
This process of curve-fitting has led to many analytic expressions that have been used in the industry over the years. It is important for the user of such curves to understand the approximations in these mathematical expressions. To obtain a good fit over a large range of physical dimensions, curve-fitting often needs to be skewed to give good results for certain parameters or to be used in analysis for specific needs. For instance, we have seen the various capacitive components in Figure 3.4 and in a simpler model in Figure 3.5. These capacitances are due to different physical phenomena. Because of this, each one varies differently with the process variables and layout parameters.
When we use curve-fitting, do we find a good fit for every one of these capacitances or do we use it to model a particular physical phenomenon as closely as possible? If we are analyzing the time delay properties of a connector, we will want to use curve-fitting to find the total capacitive loading on a connector. If we are making an analysis for signal integrity, we will want to use curve-fitting for coupling capacitances to maximize the accuracy for coupling between connectors.
As interconnects started to affect the performance of VLSI chips, the first effects on the chip related to its timing, due to time delays coming from the interconnects. Because of the time delay focus, most of the curve-fitting done to determine parasitic capacitances was until very recently for the total capacitive loading on interconnects. Consequently, most published analytical expressions are accurate for the total capacitive loading and the time delay, but not for coupling between interconnects [9,14]. This was probably acceptable for the state of the technology at the time these results were published.
However, for layout optimization, often with a focus on minimizing cross-coupling to maintain signal integrity, the coupling capacitance as a function of the proximity of the nearest neighbors may be just as important. Especially, as minimum dimensions on chips continue to shrink and supply voltages for chips continue to be reduced because of problems with power dissipation, signal integrity becomes, increasingly an issue. Smaller power supply voltages mean smaller signal amplitudes in chips, making them more vulnerable to noise and coupling.
With the current rapidly changing technologies, constant evaluations of approximations used in analytical expressions for capacitive components are needed. The most accurate analytical expressions used for today's most advanced processes are most certainly refinements of the published data of the past years. Unfortunately, many of them are proprietary and not accessible to outsiders.
One word about the enormous investment of computer resources required to generate accurate data for the processes and electrical parameters required for an analysis and optimization of layouts. This investment continuously adds to a manufacturer's knowledge base and supports the continuous development of better and better processes and models with which customers can analyze their designs. It is, therefore, well worth the effort.
Figure 3.4 shows the capacitances that affect the interconnect in the center. For the coming discussion on timing and cross-coupling, we will assume a structure as depicted in Figure 3.4 with the interconnect in the center being driven by a signal source. The dominant capacitances are the center interconnect capacitance to the substrate, the cross-coupling capacitance to the nearest neighbors and the nearest neighbors' capacitances to the substrate. For curve fitting, it may be useful to focus on certain physical effects, one at a time. For time delays and dynamic power consumption, the total capacitive loading on the center interconnect is important. The individual capacitances in Figure 3.4 should be examined, focusing just on cross-coupling and signal integrity issues.
For the following discussions on layout optimization, we will focus on parameters that can be varied with layout manipulations. Since we are interested primarily in postlayout optimization, the choice of geometries that can be manipulated is even more limited. The only interconnect parameters we can change are the width, the shape of an interconnect somewhat and the proximity to other interconnects. Of course, we can also and will change the dimensions of active devices. However, we will focus the discussion for now on interconnects.
In following discussions, we start with timing issues for digital circuits.