Since migration is generally done to move to a more advanced processing technology for the purpose of improving the performance of the circuit, the layout dimensions most critical for improving performance should become as small as allowed by the new process. The area of the migrated layout should also become as small as possible, because this minimizes parasitic elements such as parasitic capacitances and smaller chips are more cost effective. This overall reduction in size generally speeds up the circuits, a desired goal.
At the same lime, however, one of the key goals of IP reuse is to minimize or even eliminate the amount of rework on a chip after migration. After all, improvement of productivity and time-to-market are some of the key motivators for IP reuse. In other words, the chip should work as before, just faster, have a smaller footprint and, it is hoped, even use less power. While maximizing speed and achieving other desired features, the changes in the layout parameters should not render the chip nonfunctional. Timing is one of the major concerns.
Of course, Hard IP migration or Hard IP engineering can only affect chip performance parameters to the extent that they depend on physical layout dimensions. Hard IP engineering has become such a powerful tool, largely due to the DSM-technology-induced layout dependency of chip performance.
To maximize the chances of a fully functional migrated chip, at least the following criteria will have to be satisfied by migration. Some of them are satisfied automatically by the migration process; other criteria have to be met through proper specification of certain parameters:
We will now examine the four points above in more detail.
As we suggested in Chapter 1, migrating a chip does not change the chip's topology. With an unchanged topology, the netlist and, therefore, the functionality of the migrated chip remain unchanged. The functionality is unchanged because, when migrating a layout from one process to another, polygons are only shifted according to the new design rules and other specified constraints, as indicated by the user. The polygon edges move either closer together or farther apart, but they can not “jump over each other.” For this reason, connections from any element in the layout to any other do not change.
Because of this functional equivalence, the functional simulation and test vectors existing for the “old” chip can be used for the migrated chip. This is substantial, since simulation vector and test vector generation are both extremely time-consuming and costly.
What does this mean for correct functionality?
For correct functionality, the migrated chip is neither more or less functionally correct than the premigration chip. It is well known that neither functional simulation nor fault simulation guarantee a functionally correct chip. Nothing can be done with migration to improve the chances of a functionally correct chip.
What does this mean for a correct chip timing?
As opposed to guaranteeing functional equivalence, migration can not guarantee timing equivalence. We will discuss this later. However, die good news is that migration can fix timing problems, whether they are new problems or existed in the premigration chip.
If all the processing rules were entered correctly in the processing file, the migration software will guarantee correct target process design rules in the migrated chip. Since entering process design rules in the process file is a manual operation, it is prone to error. However, correctness of the processing file can be tested by migrating only a small part of the layout. This is much more efficient than having to verify an entire layout and problems in the processing file can be corrected literally “on the fly.” Once the processing file is proven correct, the correctness of the migrated layout, the migrated chip, will be design rule correct, even if the “old” chip has had some minor known or unknown violations of the layout rules. The most obvious rules to be specified are the processing-based physical layout rules. We will focus on the ones that pertain to and are required for Hard IP migration.
Processing rules reflect the limits of the processing capability to achieve the highest possible chip layout density with an acceptable manufacturing yield. These processing rules focus on what is possible in terms of processing, such as optical resolution, etching resolution, diffusion limits, ion implant limits and much more. As such, improvements in processing technology aim at improving performance or easing the manufacturing of chips. However, performance of a processing technology is not measured by the resulting speed of circuits, because the speed of a certain chip depends both on the process and design techniques. Performance of processes is measured by the minimum achievable dimensions of certain layout geometries, which are considered critical.
Smaller minimum critical dimensions have, traditionally resulted in higher speed performance circuits, especially for the active devices. Although smallness in layout geometry is still crucial to achieve high speed, other potentially more critical issues concerning layout geometry are playing an increasingly important role in determining speed and other critical chip parameters. We examine these issues in more detail in Chapter 3 when we discuss optimization and in Chapter 5 when we discuss DfM.
However, irrespective of the question of speed, smaller dimensions still mean an increase in the number of functions that can be squeezed onto a chip. The number of possible devices that can be placed on a chip is also growing, because larger and larger chips can be successfully fabricated.
The secret to setting minimum allowable layout dimensions is to adjust them so that chips can get larger and still be manufactured in volume with an acceptable yield, in conjunction with an increasingly cleaner and better controlled processing environment.
Of course, what is an acceptable yield depends on many factors. Some of these factors are trade-offs between the cost of processing, the complexity of a chip and how much can be charged for it, the manufacturing volume required at the time, what the competition is doing, etc.. In addition, special adjustments are made in a processing line to achieve the best possible performance, depending on the desired final product. This means that a process for the fabricationp of, for instance, DRAMS will be tweaked differently than one in which, microprocessors are the desired product.
So, what is an acceptable yield and/or performance for a certain chip complexity or a certain production volume may not be for another. Since many of the potential yield and performance problems encountered are related to layout, Hard IP migration is a way to directly address and minimize such problems.
By just focusing on layout and Hard IP migration, the number of rules required to specify horizontal geometry, i.e. layout rules, turns out to be quite small and conceptually simple. Of course, with the evolution of processing farther into the area of DSM, more complex rules will most probably emerge. There is consequently no need to look into all the intricacies and details specified in a foundry-generated processing manual. We focus only on all the important ones for the Hard IP migration task to be performed.
Layout rules/dimensions specified for Hard IP migration are:
Some of the more esoteric rules, such as antenna rules and minimum area rules, also need to be considered.