With the increasing importance of interconnect a great deal of information needs to flow between design tools. There are some de facto standards that we shall look at next. Some of the companies involved are working toward releasing these formats as IEEE standards.
In Section 13.5.6, “SDF in Simulation,” we discussed the structure and use of the standard delay format ( SDF) to describe gate delay and interconnect delay. We may also use SDF with floorplanning and synthesis tools to back-annotate an interconnect delay. A synthesis tool can use this information to improve the logic structure. Here is a fragment of SDF:
In this example the rising and falling delay is 60 ps (equal to 0.6 units multiplied by the time scale of 100 ps per unit specified in a TIMESCALE construct that is not shown). The delay is specified between the output port of an inverter with instance name A.INV8 in block A and the Q input port of a D flip-flop (instance name B.DFF1 ) in block B. A '.' (period or fullstop) is set to be the hierarchy divider in another construct that is not shown.
In this case all delays from an output port to, possibly multiple, input ports have the same value (we can also specify the output port name instead of the net name to identify the net). Alternatively we can lump interconnect delay at an input port:
This PORT construct specifies an interconnect delay placed at the input port of a logic cell (in this case the CLR pin of a flip-flop). We do not need to specify the start of a path (as we do for INTERCONNECT ).
We can also use SDF to forward-annotate path delays using timing constraints (there may be hundreds or thousands of these in a file). A synthesis tool can pass this information to the floorplanning and placement steps to allow them to create better layout. SDF describes timing checks using a range of TIMINGCHECK constructs. Here is an example of a single path constraint:
This describes a constraint (keyword PATHCONSTRAINT ) for the rising and falling delays between two ports at each end of a path (which may consist of several nets) to be less than 80 ps. Using the SUM construct we can constrain the sum of path delays to be less than a specific value as follows:
The physical design exchange format ( PDEF ) is a proprietary file format used by Synopsys to describe placement information and the clustering of logic cells. Here is a simple, but complete PDEF file:
- ROOT , which is the top-level (the whole chip). The file describes the size ( x - and y -bounds), current and maximum area utilization (i.e., leaving space for interconnect), and the name of the wire-load table, ' 10mm x 10mm ', to use for this block, chosen because the chip is expected to be about 10 mm on a side.
- LEAF_1 , a block below the top level in the hierarchy. This block is to use predicted capacitances from a wire-load table named '50k gates' (chosen because we know there are roughly 50 k-gate in this block). The LEAF_1 block contains two logic cells: L1.RAM01 and L1.ALU01 .
The library exchange format ( LEF ) and design exchange format ( DEF ) are both proprietary formats originated by Tangent in the TanCell and TanGate place-and-route tools which were bought by Cadence and now known as Cell3 Ensemble and Gate Ensemble respectively. These tools, and their derivatives, are so widely used that these formats have become a de facto standard. LEF is used to define an IC process and a logic cell library. For example, you would use LEF to describe a gate array: the base cells, the legal sites for base cells, the logic macros with their size and connectivity information, the interconnect layers and other information to set up the database that the physical design tools need. You would use DEF to describe all the physical aspects of a particular chip design including the netlist and physical location of cells on the chip. For example, if you had a complete placement from a floorplanning tool and wanted to exchange this information with Cadence Gate Ensemble or Cell3 Ensemble, you would use DEF.