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15.4 Estimating ASIC Size
Table 15.3 shows some useful numbers for estimating ASIC die size. Suppose we wish to estimate the die size of a 40 kgate ASIC in a 0.35 m m gate array, threelevel metal process with 166 I/O pads. For this ASIC the minimum feature size is 0.35 m m. Thus l (onehalf the minimum feature size) = 0.35 m m/2 = 0.175 m m. Using our data and Table 15.3 , we can derive the following information. We know that 0.35 m m standardcell density is roughly 5 ¥ 10^{ –4} gate/ l ^{ 2} . From this we can calculate the gate density for a 0.35 m m gate array:
This gives the core size (logic and routing only) as
(4 ¥ 10^{ 4} gates/gate density) ¥ routing factor ¥ (1/gatearray utilization) 

4 ¥ 10^{ 4} /(4 ¥ 10^{ –4} to 4.5 ¥ 10^{ –4} ) ¥ (1 to 2) ¥ 1/(0.8 to 0.9) = 10^{ 8} to 2.5 ¥ 10^{ 8} l ^{ 2} 

TABLE 15.2 System partitioning for the Sun Microsystems SPARCstation 10. 

We shall need to add (0.175/0.5) ¥ 2 ¥ (15 to 20) = 10.5 to 21 mil (per side) for the pad heights (we included the effects of scaling in this calculation). With a pad pitch of 5 mil and roughly 166/4 = 42 I/Os per side (not counting any power pads), we need a die at least 5 ¥ 42 = 210 mil on a side for the I/Os. Thus the die size must be at least 210 ¥ 210 = 4.4 ¥ 10^{ 4} mil^{ 2} to fit 166 I/Os. Of this die area only 1.19 ¥ 10^{ 4} /(4.4 ¥ 10^{ 4} ) = 27 % (at most) is used by the core logic. This is a severely padlimited design and we need to rethink the partitioning of this system.
Table 15.4 shows some typical areas for datapath elements. You would use many of these datapath elements in floatingpoint arithmetic (these elements are large—you should not use floatingpoint arithmetic unless you have to):
 A leadingone detector with barrel shifter normalizes a mantissa.
 A priority encoder corrects exponents due to mantissa normalization.
 A denormalizing barrel shifter aligns mantissas.
 A normalizing barrel shifter with a leadingone detector normalizes mantissa subtraction.
TABLE 15.3 Some useful numbers for ASIC estimates, normalized to a 1 m m technology unless noted. 

Comment 1 

Not to be confused with minimum CAD grid size (which is usually less than 0.01 m m). 

For a 1 m m technology, 2LM ( l = 0.5 m m). Scales less than linearly with l . 

For a 1 m m technology, 2LM ( l = 0.5 m m). Scales approximately linearly with l . 

Standardcell routing factor = (cell area + route area)/cell area 

Varies widely, figure is for lowcost plastic package, approximately constant 

Varies widely, figure is for a mature, 2LM CMOS process, approximately constant 
TABLE 15.4 Area estimates for datapath functions. 2 

Most datapath elements have an area per bit that depends on the number of bits in the datapath (the datapath width). Sometimes this dependency is linear (for the multipliers and the barrel shifter, for example); in other elements it depends on the logarithm (to base 2) of the datapath width (the leading one, all ones, and zero detectors, for example). In some elements you might expect there to be a dependency on datapath width, but it is small (the comparators are an example).
The area estimates given in Table 15.4 can be misleading. The exact size of an adder, for example, depends on the architecture: carrysave, carryselect, carrylookahead, or ripplecarry (which depends on the speed you require). These area figures also exclude the routing between datapath elements, which is difficult to predict—it will depend on the number and size of the datapath elements, their type, and how much logic is random and how much is datapath.
Figure 15.3 (a) shows the typical size of SRAM constructed on an ASIC. These figures are based on the use of a RAM compiler (as opposed to building memory from flipflops or latches) using a standard CMOS ASIC process, typically using a sixtransistor cell. The actual size of a memory will depend on (1) the required access time, (2) the use of synchronous or asynchronous read or write, (3) the number and type of ports (read–write), (4) the use of special design rules, (5) the number of interconnect layers available, (6) the RAM architecture (number of devices in RAM cell), and (7) the process technology (active pullup devices or pullup resistors).
The maximum size of SRAM in Figure 15.3 (a) is 32 kbit, which occupies approximately 6.0 ¥ 10^{ 7 } l ^{ 2} . In a 0.5 m m process (with l = 0.25 m m), the area of a 32 kbit SRAM is 6.0 ¥ 10^{ 7} ¥ 0.25 ¥ 0.25 = 3.75 ¥ 10^{ 6} m m^{ 2} (or about 2 mm on a side—a large piece of silicon). If you need an SRAM that is larger than this, you probably need to consult with your ASIC vendor to determine the best way to implement a large onchip memory. Figure 15.3 (b) shows the typical sizes for multipliers. Again the actual multiplier size will depend on the architecture (Booth encoding, Wallace tree, and so on), the process technology, and design rules. Table 15.5 shows some estimated gate counts for mediumsize functions corresponding to some popular ASSP devices.
Universal synchronous/asynchronous receiver/transmitter (USART) 

Source: Fujitsu channelless gatearray data book, AU and CG21 series. 
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