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# 13.3 Logic Systems

Digital signals are actually analog voltage (or current) levels that vary continuously as they change. Digital simulation assumes that digital signals may only take on a set of logic values (or logic states —here we will consider the two terms equivalent) from a logic system . A logic system must be chosen carefully. Too many values will make the simulation complicated and slow. With too few values the simulation may not accurately reflect the hardware performance.

A two-value logic system (or two-state logic system) has a logic value '0' corresponding to a logic level 'zero' and a logic value '1' corresponding to a logic level 'one'. However, when the power to a system is initially turned on, we do not immediately know whether the logic value of a flip-flop output is '1' or '0' (it will be one or the other, but we do not know which). To model this situation we introduce a logic value 'X' , with an unknown logic level, or unknown . An unknown can propagate through a circuit. For example, if the inputs to a two-input NAND gate are logic values '1' and 'X' , the output is logic value 'X' or unknown. Next, in order to model a three-state bus, we need a high-impedance state . A high-impedance state may have a logic level of 'zero' or 'one', but it is not being driven—we say it is floating. This will occur if none of the gates connected to a three-state bus is driving the bus. A four-value logic system is shown in Table 13.2 .

## 13.3.1 Signal Resolution

What happens if multiple drivers try to drive different logic values onto a bus? Table 13.3 shows a signal-resolution function for a four-value logic system that will predict the result.

TABLE 13.3 A resolution function R {A, B} that predicts the result of two drivers simultaneously attempting to drive signals with values A and B onto a bus. |
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A resolution function, R {A, B}, must be commutative and associative . That is,

R {A, B} = R {B, A} and R {R {A, B}, C} = R {A, R {B, C}}.(13.4)

Equation 13.4 ensures that, if we have three (or more) signals to resolve, it does not matter in which order we resolve them. Suppose we have four drivers on a bus driving values '0' , '1' , 'X' , and 'Z' . If we use Table 13.3 three times to resolve these signals, the answer is always 'X' whatever order we use.

## 13.3.2 Logic Strength

In CMOS logic we use n -channel transistors to produce a logic level 'zero' (with a forcing strength) and we use p -channel transistors to force a logic level 'one'. An n -channel transistor provides a weak logic level 'one'. This is a new logic value, a resistive 'one' , which has a logic level of 'one', but with resistive strength . Similarly, a p -channel transistor produces a resistive 'zero' . A resistive strength is not as strong as a forcing strength. At a high-impedance node there is nothing to keep the node at any logic level. We say that the logic strength is high impedance . A high-impedance strength is the weakest strength and we can treat it as either a very high-resistance connection to a power supply or no connection at all.

With the introduction of logic strength, a logic value may now have two properties: level and strength. Suppose we were to measure a voltage at a node
N
with a digital voltmeter (with a very high input impedance). Suppose the measured voltage at node
N
was 4.98 V (and the measured positive supply,
V
_{
DD}
= 5.00 V). We can say that node
N
is a logic level 'one', but we do not know the logic strength. Now suppose you connect one end of a 1 k
W
resistor to node
N
, the other to GND, and the voltage at
N
changes to 4.95 V. Now we can say that whatever is driving node
N
has a strong forcing strength. In fact, we know that whatever is driving
N
is capable of supplying a current of at least 4.95 V / 1 k
W
⊕ 5 mA. Depending on the logic-value system we are using, we can assign a logic value to
N
. If we allow all possible combinations of logic level with logic strength, we end up with a matrix of logic values and logic states.
Table 13.4
shows the 12 states that result with three logic levels (zero, one, unknown) and four logic strengths (strong, weak, high-impedance, and unknown). In this logic system, node
N
has logic value
S1
—a logic level of 'one' with a logic strength of 'strong'.

The Verilog logic system has three logic levels that are called '1' , '0' , and 'x' ; and the eight logic strengths shown in Table 13.5 . The designer does not normally see the logic values that result—only the three logic levels.

The IEEE Std 1164-1993 logic system defines a variable type, std_ulogic , with the nine logic values shown in Table 13.6 . When we wish to simulate logic cells using this logic system, we must define the primitive-gate operations. We also need to define the process of VHDL signal resolution using VHDL signal-resolution functions . For example, the function in the IEEE Std_Logic_1164 package that defines the and operation is as follows 1 :

function "and"(l,r : std_ulogic_vector) return std_ulogic_vector is

alias lv : std_ulogic_vector (1 to l'LENGTH ) is l;

alias rv : std_ulogic_vector (1 to r'LENGTH ) is r;

variable result : std_ulogic_vector (1 to l'LENGTH );

constant and_table : stdlogic_table := (

-----------------------------------------------------------

-----------------------------------------------------------

( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |

( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |

( '0', '0', '0', '0', '0', '0', '0', 'U', '0' ), -- | 0 |

( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |

( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |

( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |

( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |

( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |

( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | - |);

if (l'LENGTH /= r'LENGTH) then assert false report

"arguments of overloaded 'and' operator are not of the same

result(i) := and_table ( lv(i), rv(i) );

If a = 'X' and b = '0' , then (a and b) is '0' no matter whether a is, in fact, '0' or '1' .

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