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12.14 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
 a. (30 min.) Build a DesignWorks (or use another tool) model for the schematic in Figure 12.1 and simulate the operation of this circuit to check that it performs the same function as the Verilog code. Hint: You could also use VeriWell to simulate the Verilog netlist.
 b. (30 min.) Simulate the schematic (or the Verilog netlist) shown in Figure 12.2 and check that it performs the comparator/MUX function correctly.
 c. (30 min.) Simulate the schematic (or the Verilog netlist) of Figure 12.3 . If you have access to a logic synthesizer and cell library, you might resynthesize the comparator/MUX and compare the results with those shown in Figures 12.2 and 12.3 .
 d. (20 min.) Build a schematic (or Verilog model) for macro cm8 in Figure 12.4 .
 e. (30 min.) Simulate the schematic (or Verilog netlist) shown in Figure 12.4 .
12.2 (*Verilog assignments, 15 min.) Simulate and test the following model paying attention to initialization. Attempt to synthesize it. Explain your results.
parameter width = 1, reset_value = 0; input [width  1 : 0] D;
output [width  1 : 0] Q; reg [width  1 : 0] Q; input Clk,Rst;
always @ ( posedge Clk or negedge Rst )
if ( Rst == 0 ) Q <= #1 reset_value; else Q <= #1 D;
12.3 (Digital filter) (30 min.) Write HDL code to model the following filter:
y0 <= c(0) * x(0) + c(1) * x(1) + b(2) * x(2) ;
Use c(0) = 4 , c(0) = +5 , c(0) = 3 , but make your code flexible so that these coefficients may be changed. (120 min.) Simulate, test, and synthesize your model. Hint: You should use the transfer equation in your code (Verilog or VHDL).
12.4 (Hand design, 60 min.) Use hand calculation and gate delay values obtained from a data book to estimate the critical path of the comparator/MUX shown in Figure 12.1 . Assume the critical path (the one with the longest delay) is from the a[2] input (the input with the largest load) > XOR > inverter > fourinput NAND > threeinput OR > select input of twoinput MUX (the symbol > means “through the”). You will need to find the t_{ PHL} (falling) and t_{ PLH} (rising) propagation delays for each gate used in the critical path. Do not adjust the delays for the loading (fanout) at the output of each gate on the critical path, assume a loading equal to one input of a twoinput NAND gate. Change the AND–NOR gate combination to a NAND–NAND gate combination and recalculate the critical path delay.
12.5 (Critical path, 30 min.) Enter the schematic shown in Figure 12.1 and, using a gatelevel simulator or a timing analyzer, obtain the delays from the a and b inputs to the outputs. What is the critical path?
12.6 (Verilog sensitivity list, 30 min.) Simulate the following Verilog module with the test pattern shown and explain your results.
module and2_bad(a, b, c); input a, b; output c; reg c;
// test pattern: (a b) = (1 1) (0 1) (0 0) (1 0) (1 1)
Can you synthesize this module as it is? What is the error message if you get one? If you can synthesize this module as it is, simulate the synthesized logic and compare the output with the Verilog simulation.
12.7 (Verilog decoder, 30 min.) Synthesize the following Verilog module with minimumarea constraint and then with maximumspeed constraint. Compare the resulting logic in each case.
module Decoder4_to_16(Enable, In_4, Out_16);
input Enable; input [3:0] In_4; output [15:0] Out_16;
if (Enable == 1) begin Out_16 = 16'h0000; Out_16[In_4] = 1; end
What happens if you change the if statement to if (Enable === 1) ?
12.8 (Verilog eightinput MUX, 20 min.) Synthesize the following code with maximumspeed constraint and then minimumarea constraint. Compare the results.
module Mux8_to_1(InBus, Select, OutEnable, OutBit);
input [7:0] InBus; input [2:0] Select; input OutEnable;
always @(OutEnable or Select or InBus)
if (OutEnable == 1) OutBit = InBus[Select]; else OutBit = 1'bz;
12.9 (Verilog parity generator, 30 min.) Synthesize the following code with maximumspeed constraint and then minimumarea constraint. Compare the results.
module Parity (BusIn, ParityB);
input [8:0] BusIn; output ParityB; reg ParityB;
always @(BusIn) if (^Busin == 0 ) ParityB = 1; else ParityB = 0;
12.10 (Verilog edges and levels, 30 min.) What is the function of the following model? List the cells produced by a logic synthesizer, their function, and an explanation of why they were synthesized.
module DD(D, C, R, Q, QB); input D, C, R; output Q, QB; reg Q, QB, L;
always @( posedge C or posedge R) if (R == 1) L = 0; else L = D;
always @(L) begin Q = L; QB = ~L; end
12.11 (Verilog adders, 120 min.) Synthesize the following code with maximumspeed constraint and then minimumarea constraint. What type of adder architecture does the synthesis tool produce in each case (ripplecarry, lookahead, etc.)? Show exactly how you reached your conclusion. If you can, use either synthesis tool directives, shell commands, or standard components (Synopsys DesignWare or Xilinx XBLOX, for example) to direct the synthesis tool to a specific adder implementation. Check that when you optimize the synthesized logic the adder architecture is not broken up. Next, if you can, find a way to make the synthesis tool break up the adder and reoptimize the logic. Does anything change?
input [3:0] a; input [3:0] b; output [3:0] outp; reg [3:0] outp;
// if you can, change the next line to drive your synthesis tool
// pragmacompasssynopsyswhatever max_delay constraint
outp <= a + b; // Map me to DesignWare, XBlox etc., if you can.
12.12 (Elementary gates in Verilog, 60 min.) Synthesize and optimize the following (you will have to write some more code to go around these statements):
And3 = &{In1,In2,In3}; Or3 = {In1,In2,In3}; Xor3 = ^{In1,In2,In3};
This should produce threeinput AND, OR, and XOR gates. Now synthesize and optimize eightinput AND, OR, and XOR gates in the same way with minimumarea constraint and then maximumspeed constraint. Compare your results. How and why do the synthesis results and your answers change if you place a large capacitive load on the outputs. Hint: Try a load equivalent to 16 minimumsize inverters. Can you explain these results using logical effort?
12.13 (Synthesizable VHDL, 20 min.) Complete the following code fragment and try to synthesize the VHDL:
Phase <= "0" after 0 ns; Phase <= "1" after 10 ns;
What is the error message? Synthesize this code, and explain the results:
when '0' => Phase <= '1'; when others => Phase <= '0';
12.14 (VHDL and process sensitivity list, 15 min.) Simulate the following code with the test input vectors shown:
entity AND2 is port (a, b in : BIT; c out : BIT); end AND2;
architecture Bad_behavior of AND2 is begin
test inputs: (a b) = (1 1) (0 1) (0 0) (1 0) (1 1)
process (a) begin c <= a and b; end process ;
Now try to synthesize this code. Do you get an error message? If not, try simulating the synthesized logic and compare with your earlier simulation results.
12.15 (MUX logic, 20 min.) Synthesize the following VHDL:
port (InBus : in BIT_VECTOR(3 downto 0);
Sel : in BIT_VECTOR(1 downto 0);
architecture Synthesis_1 of MuxLogic is
when "00" => OutBit <= not (InBus(0));
when "01" => OutBit <= InBus(1) and InBus(2);
when "10" => OutBit <= InBus(2) or InBus(1);
when "11" => OutBit <= InBus(3) xor InBus(0);
Does the synthesizer implement the case statement using a MUX? Explain your answer carefully by using the synthesis reports and the synthesized netlist. Try synthesizing again with minimumarea constraint and then maximumspeed constraint. Does this alter the implementation chosen by the synthesis tool? Explain.
12.16 (Arithmetic overflow in VHDL) Synthesize the following model (you will need arithmetic packages):
entity Adder1 is port (InBusA,
InBusB : in Std_logic_vector(3 downto 0);
OutBus : out Std_logic_vector(3 downto 0));
architecture Behavior of Adder1 is begin OutBus <= InBusA + InBusB;
Repeat the synthesis with the following modification and explain the difference:
OutBus : out Std_logic_vector(4 downto 0));
Finally, make the following additional modification and explain all your results:
OutBus <= ( "0" & InBusA) + ("0" & InBusB) ;
12.17 (Verilog integers, 30 min.) Consider the following Verilog module:
module TestIntegers (clk, out)
integer i; reg [1:0] out; input clk; output out;
always @( posedge clk) begin i = i + 1; out = i; end
Write a test module for TestIntegers and simulate the behavior. Try to synthesize TestIntegers and explain what happens.
12.18 (Verilog shift register, 30 min.) Consider this code for a shift register:
module Shift1 (clk, q0, q1, q2)
input clk, q0; output q2, q1; reg q2, q1;
always (@ posedge clk) q1 = q0; always (@ posedge clk) q2 = q1;
Write a module Test to exercise this module. Does it simulate correctly? Can you synthesize your code for Shift1 as it is? Change the body of the code as follows (call this module Shift2 ):
always (@ posedge clk) q1 = #1 q0; always (@ posedge clk) q2 = #1 q1;
Does this simulate correctly? Now change the code as follows ( Shift3 ):
always (@ posedge clk) begin q1 = q0; q2 = q1; end
Does this simulate correctly? Can you synthesize Shift3 ? Finally, change the code to the following ( Shift4 ):
always (@ posedge clk) q1 <= q0; always (@ posedge clk) q2 <= q1
Does this simulate correctly? Can you synthesize Shift4 ?
12.19 (Reset, 20 min.) Use simulation results to explain the difference between:
always (@ posedge clk) if (clr) Q = 0;
always (@ posedge clk) if (rst) Q = 1;
always (@ posedge clk) begin if (clr) Q = 0; if (rst) Q = 1; end
12.20 (Verilog assignments, 30 min.) Consider the following Verilog module:
module TestAssign1(sel) input sel; reg outp;
always @sel begin outp <= 1; if (sel) outp <= 0; end
Write a module to drive TestAssign1 and simulate your code. Now consider the following modification (call this TestAssign2 ):
if (sel) outp <= 0; else outp <= 1;
Simulate TestAssign2 and compare your results. Try to synthesize TestAssign1 and TestAssign2 . Comment on any problems you have and how you resolved them. Compare the behavior of the synthesized logic with the simulations.
12.21 (VHDL sequential logic, 60 min.) Consider the following processes:
if clk'EVENT and clk = '1' then count <= count + inc; end if ;
elsif clk'EVENT and clk = '1' then count <= count + inc;
if rst = '1' then count <= 0; elsif clk'EVENT and clk = '1' then
count <= count + inc; sum <= count + sum;
if clk'EVENT and clk = '1' then if rst = '1' then count <= 0;
else count <= count + inc; end if ;
elsif clk'EVENT and clk = '1' then count <= count + inc;
elsif clk'EVENT and clk = '1' then count <= count + inc;
Write code to drive each of these processes and simulate them. Explain any errors or problems you encounter. Try to synthesize your code and check that the results behave correctly and match the simulation results. Explain any differences in behavior or any problems you encounter.
12.22 (Verilog signed multiplication, 30 min.) Show, by simulation, that the following code performs signed multiplication. Synthesize the code and compare the results with the simulation.
module Smpy (in1, in2, out); input [2:0] in1, in2; output [5:0] out;
assign out = {{3{in1[2]}},in1}*{{3{in2[2]}},in2};
12.23 (Verilog arithmetic, 30 min.) Synthesize the following code and explain in detail the implementation that results:
module Arithmetic (in_4, out_2, out_3, out_7, out_14);
input [3:0] in_4; output [7:0] out_2, out_3, out_7, out_14;
assign out_2 = in_4*2; assign out_3 = in_4*3; assign out_7 = in_4*7;
assign out_14 = in_4 * 4'b1110;
12.24 (Verilog overflow bit, 15 min.) Synthesize the following code and explain the implementation that results:
module Overflow (a, b, sum, cout);
input [7:0] a, b; output [7:0] sum; output cout;
12.25 (*VHDL latches, 60 min.) Consider the following two architectures:
entity latch1 is port (data: in BIT_VECTOR(1 to 4);
reset: in BIT; delay: out BIT_VECTOR(1 to 4));
architecture Synthesis_1 of latch1 is
begin S1: process (data, reset) variable hold : BIT_VECTOR (1 to 4);
if reset = '1' then hold := "0000"; end if ;
architecture Synthesis_2 of latch1 is
begin S2: process (data, enable, reset)
variable hold : BIT_VECTOR (1 to 4);
if enable = '1' then hold := data; end if ;
if reset = '0' then hold := "0000";
Try to synthesize both versions. Does the synthesizer accept the code? Hint: It should not. Explain any problems that you encounter, and how to correct them. Resynthesize your working code.
12.26 (*VHDL data slip, 60 min.) Consider the following process, a shift register core:
S1: process (data, enable) begin
if enable = '1' then Q <= Q(7 downto 0) & data; end if ;
Complete the VHDL code and simulate to ensure your model operates correctly. Try to synthesize your code and compare the operation of the resulting implementation with the simulation results. Explain any problems you encounter.
12.27 (**Synchronous logic, hours) Investigate the following alternative ways to synthesize synchronous logic in VHDL. Hint: A few of these methods are illegal in both VHDL87 and VHDL93, some methods are only illegal in VHDL87. Create a table for Q1Q17 that summarizes your results. Assume all signals are STD_LOGIC . Can you create any more methods (positiveedge only)?
 Let me count the ways to count.
process begin wait on clk; Q1 <= D; end process ;  2 edges
process begin wait on clk until clk = '1'; Q2 <= D; end process ;
process begin wait until clk = '1'; Q3 <= D; end process ;
process begin wait until clk = '1' and clk'EVENT; Q4 <= D;
 Using process and sensitivity list:
process (clk) begin if clk'EVENT and clk = '1' then Q5 <= D; end if ;
process (clk) begin if not clk'STABLE and clk = '1' then Q6 <= D;
if clk'LAST_VALUE = '0' and clk = '1' then Q7 <= D; end if ;
 Using rising_edge function from STD_LOGIC_1164:
process (clk) begin if rising_edge(clk) then Q8 <= D; end if ;
process begin wait until rising_edge(clk); Q9 <= D; end process ;
process begin wait on rising_edge(clk); Q10 <= D; end process ;
if clk'EVENT and To_X01(clk) = '1'
and To_X01(clk'LAST_VALUE) = '0' then Q11 <= D; end if ;
 Using concurrent signal assignments:
Q12 <= D when clk'EVENT and clk = '1';  VHDL93 only (...else)
Q13 <= D when clk'EVENT and clk = '1' else Q13;  need buffer
Q14 <= D when clk'EVENT and clk = '1' else unaffected ;  VHDL93
Q15 <= D when clk'EVENT and clk = '1'
else Q15'DRIVING_VALUE;  VHDL93
F1: block ( not clk'STABLE and clk = '1')
begin Q16 <= guarded D; end block ;
F2: block (clk'EVENT and clk = '1')
begin Q17 <= guarded D; end block ;
 The bizarre and variations using '0', 'L', 'H', and '1':
if clk'LAST_VALUE = 'L' and clk = 'H' or clk = '1' then Q18 <= D;
process begin wait until clk = 'H' or clk = '1';
12.28 (*State assignment, 30 min) If we have a state machine with r states and S _{ 0} variables, how many different state assignments are there, for S _{ 0} = 1 and r = 2? List the different state assignments with S _{ 0} = 2, r = 3 and for S _{ 0} = 2, r = 4. How many of these are distinct? For five states and three state variables there are 6720 different state assignments, of which 140 are distinct. For nine states and four state variables there are over 4 ¥ 10^{ 9} different possible state assignments and nearly 11 million of these are distinct. This makes the task of performing sequential logic synthesis by exhaustively considering all possible state assignments virtually impossible. Hint: McCluskey’s book discusses the problem of state assignment [ 1965, pp. 266–267].
12.29 (*Synthesis scripts, hours) Write and document a script to synthesize the Viterbi decoder using a logic synthesizer of your choice.
12.30 (*Floorplanning, hours) Write and document a script to perform timingdriven synthesis and floorplanning for the Viterbi decoder.
12.31 (***Patents, 120 min.) Obtain a copy of U.S. Patent 5,530,841 “Method for converting a hardware independent user description of a logic circuit into hardware components.” This patent caused controversy during the approval of the IEEE synthesis packages. Research this topic (including a visit to the Web site of the synthesis package working group and checking other synthesis patents). Do you feel (as an engineer) that the IEEE should be concerned?
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