ShareCG: ASICs .. the Book
ASICs Chapter 11: Verilog HDL

Back to index of chapters


In this chapter we look at the Verilog hardware description language. Gateway Design Automation developed Verilog as a simulation language. The use of the Verilog-XL simulator is discussed in more detail in Chapter 13. Cadence purchased Gateway in 1989 and, after some study, placed the Verilog language in the public domain. Open Verilog International (OVI) was created to develop the Verilog language as an IEEE standard. The definitive reference guide to the Verilog language is now the Verilog LRM, IEEE Std 1364-1995 [1995]. 1 This does not mean that all Verilog simulators and tools adhere strictly to the IEEE Standard--we must abide by the reference manual for the software we are using. Verilog is a fairly simple language to learn, especially if you are familiar with the C programming language. In this chapter we shall concentrate on the features of Verilog applied to high-level design entry and synthesis for ASICs.


11.1   A Counter

11.2   Basics of the Verilog Language

11.3   Operators

11.4   Hierarchy

11.5   Procedures and Assignments

11.6   Timing Controls and Delay

11.7   Tasks and Functions

11.8   Control Statements

11.9   Logic-Gate Modeling

11.10   Modeling Delay

11.11   Altering Parameters

11.12   A Viterbi Decoder

11.13   Other Verilog Features

11.14   Summary

11.15   Problems

11.16   Bibliography

11.17   References

1. Some of the material in this chapter is reprinted with permission from IEEE Std 1364-1995, © Copyright 1995 IEEE. All rights reserved.

© 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us
ShareCG™ is a trademark of Internet Business Systems, Inc.

Report a Bug Report Abuse Make a Suggestion About Privacy Policy Contact Us User Agreement Advertise