ShareCG: ASICs .. the Book

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4.6  PREP Benchmarks

Which type of FPGA is best? This is an impossible question to answer. The Programmable Electronics Performance Company ( PREP ) is a nonprofit organization that organized a series of benchmarks for programmable ASICs. The nine PREP benchmark circuits in the version 1.3 suite are:

  1. An 8-bit datapath consisting of 4:1 MUX, register, and shift-register
  2. An 8-bit timer–counter consisting of two registers, a 4:1 MUX, a counter and a comparator
  3. A small state machine (8 states, 8 inputs, and 8 outputs)
  4. A larger state machine (16 states, 8 inputs, and 8 outputs)
  5. An ALU consisting of a 4 ¥ 4 multiplier, an 8-bit adder, and an 8-bit register
  6. A 16-bit accumulator
  7. A 16-bit counter with synchronous load and enable
  8. A 16-bit prescaled counter with load and enable
  9. A 16-bit address decoder

The data for these benchmarks is archived at . PREP’s online information includes Verilog and VHDL source code and test benches (provided by Synplicity) as well as additional synthesis benchmarks including a bit-slice processor, multiplier, and R4000 MIPS RISC microprocessor.

One problem with the FPGA benchmark suite is that the examples are small, allowing FPGA vendors to replicate multiple instances of the same circuit on an FPGA. This does not reflect the way an FPGA is used in practice. Another problem is that the FPGA vendors badly misused the results. PREP made the data available in a spreadsheet form and thus inadvertently challenged the marketing department of each FPGA vendor to find a way that company could claim to win the benchmarks (usually by manipulating the data using a complicated weighting scheme). The PREP benchmarks do demonstrate the large variation in performance between different FPGA architectures that results from differences in the type and mix of logic. This shows that designers should be careful in evaluating others’ results and performing their own experiments.

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