Logic-cell delay results from transistor resistance, transistor (intrinsic) parasitic capacitance, and load (extrinsic) capacitance. When one logic cell drives another, the parasitic input capacitance of the driven cell becomes the load capacitance of the driving cell and this will determine the delay of the driving cell.
Figure 3.4 shows the components of transistor parasitic capacitance. SPICE prints all of the MOS parameter values for each transistor at the DC operating point. The following values were printed by PSpice (v5.4) for the simulation of Figure 3.3 :
NAME m1 m2
MODEL CMOSN CMOSP
ID 7.49E-11 -7.49E-11
VGS 0.00E+00 -3.00E+00
VDS 3.00E+00 -4.40E-08
VBS 0.00E+00 0.00E+00
VTH 4.14E-01 -8.96E-01
VDSAT 3.51E-02 -1.78E+00
GM 1.75E-09 2.52E-11
GDS 1.24E-10 1.72E-03
GMB 6.02E-10 7.02E-12
CBD 2.06E-15 1.71E-14
CBS 4.45E-15 1.71E-14
CGSOV 1.80E-15 2.88E-15
CGDOV 1.80E-15 2.88E-15
CGBOV 2.00E-16 2.01E-16
CGS 0.00E+00 1.10E-14
CGD 0.00E+00 1.10E-14
CGB 3.88E-15 0.00E+00
The parameters ID ( I DS ), VGS , VDS , VBS , VTH (V t ), and VDSAT (V DS (sat) ) are DC parameters. The parameters GM , GDS , and GMB are small-signal conductances (corresponding to ∂ I DS /∂ V GS , ∂ I DS /∂ V DS , and ∂ I DS /∂ V BS , respectively). The remaining parameters are the parasitic capacitances. Table 3.1 shows the calculation of these capacitance values for the n -channel transistor m1 (with W = 6 m m and L = 0.6 m m) in Figure 3.3 (a).
The junction capacitances, C BD and C BS , consist of two parts: junction area and sidewall; both have different physical characteristics with parameters: CJ and MJ for the junction, CJSW and MJSW for the sidewall, and PB is common. These capacitances depend on the voltage across the junction ( V DB and V SB ). The calculations in Table 3.1 assume both source and drain regions are 6 m m ¥ 1.2 m m rectangles, so that A D = A S = 7.2 ( m m) 2 , and the perimeters (excluding the 1.2 m m channel edge) are P D = P S = 6 + 1.2 + 1.2 = 8.4 m m. We exclude the channel edge because the sidewalls facing the channel (corresponding to C BSJ GATE and C BDJ GATE in Figure 3.4 ) are different from the sidewalls that face the field. There is no standard method to allow for this. It is a mistake to exclude the gate edge assuming it is accounted for in the rest of the model—it is not. A pessimistic simulation includes the channel edge in P D and P S (but a true worst-case analysis would use more accurate models and worst-case model parameters). In HSPICE there is a separate mechanism to account for the channel edge capacitance (using parameters ACM and CJGATE ). In Table 3.1 we have neglected C J GATE .
For the p -channel transistor m2 (W = 12 m m and L = 0.6 m m) the source and drain regions are 12 m m ¥ 1.2 m m rectangles, so that A D = A S ª 14 ( m m) 2 , and the perimeters are P D = P S = 12 + 1.2 + 1.2 ª 14 m m (these parameters are rounded to two significant figures solely to simplify the figures and tables).
In passing, notice that a 1.2 m m strip of diffusion in a 0.6 m m process ( l = 0.3 m m) is only 4 l wide—wide enough to place a contact only with aggressive spacing rules. The conservative rules in Figure 2.11 would require a diffusion width of at least 2 (rule 6.4a) + 2 (rule 6.3a) + 1.5 (rule 6.2a) = 5.5 l .
The overlap capacitance calculations for C GSOV and C GDOV in Table 3.1 account for lateral diffusion (the amount the source and drain extend under the gate) using SPICE parameter LD = 5E-08 or L D = 0.05 m m. Not all versions of SPICE use the equivalent parameter for width reduction, WD (assumed zero in Table 3.1 ), in calculating C GDOV and not all versions subtract W D to form W EFF .
The gate capacitance calculations in Table 3.1 depend on the operating region. The gate–source capacitance C GS varies from zero when the transistor is off to 0.5C O (0.5 ¥ 1.035 ¥ 10 –15 = 5.18 ¥ 10 –16 F) in the linear region to (2/3)C O in the saturation region (6.9 ¥ 10 –16 F). The gate–drain capacitance C GD varies from zero (off) to 0.5C O (linear region) and back to zero (saturation region).
The gate–bulk capacitance C GB may be viewed as two capacitors in series: the fixed gate-oxide capacitance, C O = W EFF L EFF e ox / T ox , and the variable depletion capacitance, C S = W EFF L EFF e Si / x d , formed by the depletion region that extends under the gate (with varying depth x d ). As the transistor turns on the conducting channel appears and shields the bulk from the gate—and at this point C GB falls to zero. Even with V GS = 0 V, the depletion width under the gate is finite and thus C GB ª 4 ¥ 10 –15 F is less than C O ª 10 –16 F. In fact, since C GB ª 0.5 C O , we can tell that at V GS = 0 V, C S ª C O .
Figure 3.5 shows the variation of the parasitic capacitance values.
FIGURE 3.5 The variation of n -channel transistor parasitic capacitance. Values were obtained from a series of DC simulations using PSpice v5.4, the parameters shown in Table 3.1 ( LEVEL=3 ), and by varying the input voltage, v(in1) , of the inverter in Figure 3.3 (a). Data points are joined by straight lines. Note that CGSOV = CGDOV .
Figure 3.6 shows an experiment to monitor the input capacitance of an inverter as it switches. We have introduced another variable—the delay of the input ramp or the slew rate of the input.
In Figure 3.6 (b) the input ramp is 40 ps long with a slew rate of 3 V/ 40 ps or 75 GVs –1 —as in our previous experiments—and the output of the inverter hardly moves before the input has changed. The input capacitance varies from 20 to 40 fF with an average value of approximately 34 fF for both transitions—we can measure the average value in Probe by plotting AVG(-i(Vin)) .
In Figure 3.6 (c) the input ramp is slow enough (300 ns) that we are switching under almost equilibrium conditions—at each voltage we allow the output to find its level on the static transfer curve of Figure 3.2 (a). The switching waveforms are quite different. The average input capacitance is now approximately 0.04 pF (a 20 percent difference). The propagation delay (using an input trip point of 0.5 and an output trip point of 0.35) is negative and approximately 150 – 127 = –23 ns. By changing the input slew rate we have broken our model. For the moment we shall ignore this problem and proceed.
The calculations in Table 3.1 and behavior of Figures 3.5 and 3.6 are very complex. How can we find the value of the parasitic capacitance, C , to fit the model of Figure 3.1 ? Once again, as we did for pull resistance and the intrinsic output capacitance, instead of trying to derive a theoretical value for C, we adjust the value to fit the model. Before we formulate another experiment we should bear in mind the following questions that the experiment of Figure 3.6 raises: Is it valid to replace the nonlinear input capacitance with a linear component? Is it valid to use a linear input ramp when the normal waveforms are so nonlinear?
Figure 3.7 shows an experiment crafted to answer these questions. The experiment has the following two steps:
- Adjust c2 to model the input capacitance of m5/6 ; then C = c2 = 0.0335 pF.
- Remove all the parasitic capacitances for inverter m9/10 —except for the gate capacitances C GS , C GD , and C GB —and then adjust c3 (0.01 pF) and c4 (0.025 pF) to model the effect of these missing parasitics.
- Since the waveforms in Figure 3.7 match, we can model the input capacitance of a logic cell with a linear capacitor. However, we know the input capacitance may vary (by up to 20 percent in our example) with the input slew rate.
- The input waveform to the inverter m3/m4 in Figure 3.7 is from another inverter—not a linear ramp. The difference in slew rate causes an error. The measured delay is 85 ps (0.085 ns), whereas our model (Eq. 3.7 ) predicts
- The total gate-oxide capacitance in our inverter with T ox = 100Å is
- All the transistor parasitic capacitances excluding the gate capacitance contribute 0.01 pF of the 0.0335 pF input capacitance—about 30 percent. The gate capacitances contribute the rest—0.025 pF (about 70 percent).
The last two observations are useful. Since the gate capacitances are nonlinear, we only see about 0.025/0.037 or 70 percent of the 0.037 pF gate-oxide capacitance, C O , in the input capacitance, C . This means that it happens by chance that the total gate-oxide capacitance is also a rough estimate of the gate input capacitance, C ª C O . Using L and W rather than L EFF and W EFF in Eq. 3.9 helps this estimate. The accuracy of this estimate depends on the fact that the junction capacitances are approximately one-third of the gate-oxide capacitance—which happens to be true for many CMOS processes for the shapes of transistors that normally occur in logic cells. In the next section we shall use this estimate to help us design logic cells.