ShareCG: ASICs .. the Book # 14.6  Scan Test

Sequential logic poses a very difficult ATPG problem. Consider the example of a 32-bit counter with a final carry. If the designer included a reset, we have to clock the counter 2 32 (approximately 4 ¥ 10 9 ) times to check the carry logic. Using a 1 MHz tester clock this requires 4 ¥ 10 3 seconds, 1 hour, or (at approximately \$0.25 per second) \$1,000 of tester time. Consider a 16-bit state machine implemented using a one-hot state register with 16 D flip-flops. If the designer did not include a reset we have a very complicated initialization problem. A sequential ATPG algorithm must consider over 2000 states when constructing sequential test vectors. In an ad hoc approach to testing we could construct special reset circuits or create manual test vectors to deal with these special situations, one at a time, as they arise. Instead we can take a structured test approach (also called design for test , though this term covers a wider field).

We can automatically generate test vectors for combinational logic, but ATPG is much harder for sequential logic. Therefore the most common sequential structured test approach converts sequential logic to combinational logic. In full-scan design we replace every sequential element with a scan flip-flop. The result is an internal form of boundary scan and, if we wish, we can use the IEEE 1149.1 TAP to access (and the boundary-scan controller to control) an internal-scan chain.

Table 14.9 shows a VHDL model and schematic symbols for a scan flip-flop. There is an area and performance penalty to pay for scan design. The scan MUX adds the delay of a 2:1 MUX to the setup time of the flip-flop; this will directly subtract from the critical path delay. The 2:1 MUX and any separate driver for the scan output also adds approximately 10 percent to the area of the flip-flop (depending on the features present in the original flip-flop). The scan chain must also be routed, and this complicates physical design and adds to the interconnect area. In ASIC design the benefits of eliminating complex sequential ATPG and the addition of observability and controllability usually outweigh these disadvantages.

 TABLE 14.9  Scan flip-flop. library IEEE; use IEEE.STD_LOGIC_1164. all ; entity DFFSCAN is generic (reset_value : STD_LOGIC := '0'); port ( Q : out STD_LOGIC ; D, CLK, RST : in STD_LOGIC; SCOUT : out STD_LOGIC; SCIN, SCEN : in STD_LOGIC ); end DFFSCAN; architecture behave of DFFSCAN is signal RST_IN, CLK_IN , SCEN_IN , SCIN_IN, D_IN : STD_LOGIC ; begin RST_IN <= to_X01(RST); CLK_IN <= to_X01(CLK); SCEN_IN <= to_X01(SCEN); SCIN_IN <= to_X01(SCIN); D_IN <= to_X01(D); DFSCAN : process (CLK_IN, RST_IN) begin if RST_IN = '0' then Q <= reset_value; SCOUT <= reset_value; elsif RST_IN = '1' and rising_edge (CLK_IN) then if SCEN_IN = '1' then Q <= SCIN_IN; SCOUT <= SCIN_IN; end if ; elsif SCEN_IN = '0' then Q <= D_IN; SCOUT <= D_IN; else Q <= 'X' ; SCOUT <= 'X'; end if ; elsif RST_IN = 'X' or CLK_IN = 'X' or SCEN_IN = 'X' then Q <= 'X'; SCOUT <= 'X'; end if ; end process DFSCAN; end behave;

The highly structured nature of full scan allows test software (usually called a test compiler ) to perform automatic scan insertion . Using scan design we turn the output of each flip-flop into a pseudoprimary input and the input to each flip-flop into a pseudoprimary output . ATPG software can then generate test vectors for the combinational logic between scan flip-flops.

There are other approaches to scan design. In partial scan we replace a subset of the sequential elements with scan flip-flops. We can choose this subset using heuristic procedures to allow the remaining sequential logic to be tested using sequential ATPG techniques. In destructive scan we remove the values at the outputs of the flip-flops during the scan process (this is the usual form of scan design). In nondestructive scan we keep the flip-flop outputs intact so that we can shift out the scan chain and then resume where we left off. Level-sensitive scan design ( LSSD ) is a form of scan design developed at IBM that uses separate clock phases to drive scan elements.

We shall describe scan design, automated scan insertion, and test-program generation with several examples. First, though, we describe another important structured-test technique.