- a. If the programming current of an antifuse is 5 mA and the link diameter that is formed is 20 nm, what is the current density during programming?
- b. If the average antifuse resistance is 500 W after programming is complete and the programming current is 5 mA, what is the voltage across the antifuse at completion of programming?
- c. What power is dissipated in the antifuse link at the end of programming?
- d. Suppose we wish to reduce the antifuse resistance from 500 W to 50 W . If the antifuse link is a tall, thin cylinder, what is the diameter of a 50 W antifuse?
- e. Assume we need to keep the power dissipated per unit volume of the antifuse link the same at the end of the programming process for both 500 W and 50 W antifuses. What current density is required to program a 50 W antifuse?
- f. With these assumptions what is the required programming current for a 50 W antifuse? Comment on your answer and the assumptions that you have made.
- a. We have stated that it takes about 5 to 10 minutes to program an Actel part. Given the number of antifuses on the smallest Actel part, and the number of antifuses that need to be blown on average, work out the equivalent time it takes to blow one antifuse. Does this seem reasonable?
- b. Because of a failure process known as electromigration, the current density in a metal wire on a chip is limited to about 50 k Acm –2 . You can exceed this current for a short time as long as the time average does not exceed the limit. Suppose we want to use a minimum metal width to connect the programming transistors: Would these facts help explain your answer to part a?
- c. What other factors might be involved in the process of blowing antifuses that may help explain your answer to part a?
- a. (30 min.) Assume the two inverters in the cross-coupled SRAM cell are minimum size (they are not, the p- channels—or n- channels—in one inverter need to be weak—long and narrow—but ignore this). Assume the read–write device is minimum size. Estimate the size of the SRAM cell including an allowance for wiring (state your assumptions clearly).
- b. (15 min.) Assume a single n- channel pass transistor is connected to the SRAM cell and has an on-resistance of 500 W (equal to the average Actel ACT 1 antifuse resistance for comparison; the actual Xilinx pass transistors have closer to 1 k W on-resistance). Estimate the transistor size. Assume the gate voltage of the pass transistor is at 5 V, and the source and drain voltages are both at 0 V (the best case). Hint: Use the parameters from Section 3.1 , “ Transistors as Resistors .”
- c. (15min.) Compare your total area estimates of the cell with other FPGA technologies. Explain why the assumptions you made may be too simple, and suggest ways to make more accurate estimates.
4.4 (FPGA vendors, 60 min.) Update the information shown in Table 4.7 using the online information provided by FPGA vendors.
4.5 (Prices) Adjustment factors, calculated from averages across the Xilinx price matrix, are shown in Table 4.8 (the adjustment factors for the Xilinx military and MIL-STD parts vary so wildly that it is not possible to use a simple model to predict these prices).
- a. (5 min.) Estimate the price of a XC3042-70PG132I in 100+ quantity, purchased in 1H92.
- b. (30min.) Use the 1992 prices in Figure 4.9 to derive as much of the information shown in Table 4.8 as you can, explaining your methods.
- c. (Hours) Construct a table (using the format of Table 4.8 ) for a current FPGA family. You may have to be creative in capturing the HTML and filtering it into a spreadsheet. Hint: In Microsoft Word 5.0 you can select columns of text by holding down the Option key.
TABLE 4.8 Xilinx price adjustment factors (1992) for Problem 4.5
4.6 (PREP benchmarks, 60min.) Download the PREP 1.3 benchmark results as spreadsheets from http://www.prep.org . Split the participating companies among groups and challenge each group to produce an averaging or analysis scheme that shows the group’s assigned company as a “winner.” For hints on this problem, consult advertisements in past issues of EE Times .
- a. Find U.S. Patent 5,440,245, Galbraith et al. “Logic module with configurable combinational and sequential blocks.” Find and explain a method to paste the figures into a report.
- b. Conduct a patent search on FPGAs. Good places to start are the U.S. Patent and Trademark Office ( PTO ) at http://www.uspto.gov and the IBM patent resource at http://patent.womplex.ibm.com . Until 1996 the full text of recent U.S. patents was available at http://www.town.hall.org/patent ; this is still a good site to visit for references to other locations. Table 4.9 lists the patents awarded to the major FPGA companies up until 1996 (in the case of Actel and Altera the list includes only patents issued after 1990, corresponding roughly to patent numbers greater than number 5,000,000, which was issued in March 1990).
4.8 (**Maskworks, days) If you really want to find out about FPGA technology you tear chips apart. There is another way. Most U.S. companies register their chips as a type of copyright called a Maskwork . You will often see a little circle containing an “M” on a chip in the same way that a copyright sign is a circle surrounding the letter “C”. Companies that require a Maskwork are required to deposit plots and samples of the chips with a branch of the Library of Congress. These plots are open for public inspection in Washington, D.C. It is perfectly legal to use this information. You have to sign a visitors’ book, and most of the names in the book are Japanese. Research Maskworks and write a summary of its implications, the protection it provides, and (if you can find them) the rules for the materials that must be deposited with the authorities.