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VHDL and AHDL Digital System Implementation
Author: Scarpino, Frank
Cover: Hard cover
Pages: 316
List Price: $62.00
Published by Prentice Hall PTR .
Date Published: 11/1997
ISBN: 0138570876
 Table of Contents
Introduction xi
Part I Theory and Applications in Altera 3
Hardware Description Language
Chapter 1 An Introduction to Combinational 3
Logic and Hardware Description Language
1.1 Introduction 3
1.2 A Combinational Logic Theorem 4
1.2.1 Combinational Theorem Using HDL 4
1.3 DeMorgan's Theorem 7
1.4 DeMorgan's Theorem and HDL 7
1.5 Implementation of a One-Bit Full Adder 8
1.6 An HDL Solution for a One-Bit Full 11
Adder
1.7 An Alternate HDL Solution for a 12
One-Bit Full Adder
1.8 An HDL Four-Bit Ripple-Carry Adder 14
1.9 An Alternate Four-Bit HDL Full Adder 17
1.9.1 Timing Analysis of a Four-Bit Adder 20
1.10 An HDL Adder/Subtractor 21
1.10.1 Additional Adder Hierarchy 22
1.11 Two-Level Logic Functions 24
1.11.1 Two-Level Nand-Nand Logical Forms 24
1.11.2 Two-Level Nor-Nor Logical Forms 26
1.12 Retrospective 28
Chapter 1 Exercises 28
Chapter 2 D-Type Memory, Basic Applications, 30
and HDL
2.1 Basics of D-Type, One-Bit Memories 30
2.2 Asynchronous Inputs 34
2.3 Building a Twisted Ring Counter with 37
D-Memories
2.4 A Reliable Twisted-Ring Counter Using 39
a Case Construction
2.5 A Reliable Twisted-Ring Counter with 40
State Decoder
2.6 A High-Speed Two-Bit Twisted-Ring 43
(Johnson) Counter
2.7 Maximum Clock Rate for a Two-Bit 44
Johnson Counter
2.8 Building a J-K Flip-Flop from a D-Type 46
Flip-Flop
2.9 Retrospective 48
Chapter 2 Exercises 49
Chapter 3 Elements of Control Logic 51
3.1 Looking Back: Control Logic for 51
Twisted-Ring Counters
3.2 A Basic Form of Control Logic for 52
D-Type Flip-Flops
3.2.1 An Eight-State Timing Generator 52
3.2.2 Controlling the State of a One 55
Bit, D-Type Flip-Flop
3.2.3 A Three D Flip-Flop Illustration 59
3.3 A Loadable, Left-Right Shift Register 60
3.4 An Alternative Source File for a 63
Load/Hold/L-R Circular Shift Register
3.5 Tri-State Control 64
3.6 A Tri-State Interface for Registers 66
3.7 Retrospective 68
Chapter 3 Exercises 69
Chapter 4 An Overview of Counting Methods 72
4.1 Introduction 72
4.2 Commentary on Twisted-Ring Counters 72
4.3 Natural Binary Counters 73
4.3.1 Manual Truth Table Design for 73
Binary Counters
4.3.2 HDL Truth Table for Binary Counters 79
4.4 Classical Nonbinary Counters 80
4.4.1 A Low-Performance Decade Counter 80
4.4.2 An Improved Decade Counter 82
4.4 A Duodecade Counter 84
4.5 Polynomial Counters 85
4.5.1 A Three-Bit Polynomial Counter 86
4.5.2 "Poly" Counters with Sequence 87
Lengths 3 through 65,535
4.5.3 Autocorrelation and Maximal Length 89
Sequences
4.5.4 Decoding Selected Vectors from a 100
"Poly" Counter
4.6 An Up-Down Counter Using Conditional 100
Tables
4.7 A Ripple Counter 102
4.8 Gray-Code Counters 106
4.9 Retrospective 109
Chapter 4 Exercises 109
Chapter 5 A Simplified UART/PC COM Port 112
Receiver
5.1 Introduction 112
5.2 UART Signal Definition 112
5.2.1 Receiver Architecture 113
5.3 Creating the Correct Interface Voltage 114
Range
5.4 Asynchronous Signal Detection 115
5.5 Sampling the Stream 118
5.5.1 Persistence in Processing 118
5.5.2 Receiver Design 121
5.5.3 Overview of Receiver Design 121
Requirements
5.5.4 Receiver Logic Design 123
5.5 Retrospective 128
Chapter 5 Exercises 128
Chapter 6 Application of 7400-Series Library 131
Functions
6.1 Introduction 131
6.2 A 74176-Presentable Decade Counter 132
6.3 A 74181 Arithmetic Logic Unit (ALU) 136
Macrofunction
6.4 A 74176 Counter/7445 Decoder Timing 142
Generator
6.5 A 74276 Library Register Macrofunction 145
6.5.1 Introduction 145
6.5.2 Using the 74276 in a Text-Design 146
File
6.5.3 Simulation 148
6.6 An Integrated Application of 148
7400-Series Circuits
6.6.1 Introduction 148
6.6.2 Text-Design File 149
6.6.3 Simulation 150
6.7 Retrospective 150
Chapter 6 Exercises 152
Chapter 7 State Machines in AHDL 154
7.1 Introduction 154
7.2 The Moore Model of a State Machine 155
7.2.1 A Simple Moore Machine 156
7.2.2 A Moore Machine Sequence Detector 158
7.3 The Mealy Model of a State Machine 161
7.3.1 A Mealy-Machine Sequence Detector 161
7.4 An FSM Monitor for a Maximal Length 164
Sequence Generator
7.4.1 Introduction 164
7.4.2 State-Machine Description 164
7.5 Retrospective 169
Chapter 7 Exercises 170
Chapter 8 Application of Parametric Modules 172
8.1 Introduction 172
8.2 An LPM Random Access Memory System 173
8.3 A Library Digital-Phase Detector 178
8.4 An LPM Four-Bit Multiplier 181
8.4.1 Direct Instantiation of an LPM 184
Multiplier
8.5 An NTSC Television-Signal Generator 187
8.5.1 Introduction 187
8.5.2 An LPM NTSC Graphic-Design File 187
8.5.3 Source File for Utilization of 188
NTSC Library Function
8.6 Retrospective 190
Chapter 8 Exercises 190
Part II Introduction to Applications in VHSIC 195
Hardware Description Language
Chapter 9 An Introduction to VHDL 195
9.1 Introduction 195
9.2 A Short Historical Note 195
9.3 A Prospective Glance 196
9.4 An Initial VHDL Counter 196
9.5 A Simple VHDL D-Type Flip-Flop 199
9.6 A Negative-Edge Triggered Flip-Flop 201
9.7 A VHDL D-Type Flip-Flop with 203
Synchronous Preset and Clear
9.8 A VHDL Flip-Flop with Active Low 205
Asynchronous Preset and Clear
9.9 A One-Bit VHDL Full Adder 207
9.10 A Four-Bit VHDL Adder 210
9.11 Retrospective 211
Chapter 9 Exercises 211
Chapter 10 A Semi-Formal Introduction to VHDL 213
10.1 Introduction 213
10.2 Three Design Methods 214
10.2.1 A DataFlow D-Type Flip-Flop 214
10.2.2 A Structural D-Type Flip-Flop 216
10.2.3 A Behavioral (Sequential) 221
Flip-Flop
10.2.4 A Clocked Behavioral D-Type 222
Flip-Flop
10.3 A VHDL, Positive-Edge Detector 224
10.4 A Behavioral Twisted-Ring Counter 228
Design
10.4.1 Twisted-Ring Counter Design 228
10.5 VHDL State Machines 231
10.5.1 Ten-Bit VHDL Polynomial and 231
Ordinal Counters
10.5.2 A VHDL FSM State Machine Monitor 233
for an m-Sequence Generator
10.6 VHDL and a Classic 74283 Adder Circuit 239
10.7 Retrospective 242
Chapter 10 Exercises 242
Chapter 11 Integer Types, User Types, 245
Arrays, and Functions in Applications
11.1 Introduction 245
11.2 Logic Vectors, Integers, and 245
Companion Counters
11.3 A Simple Integer Processor 249
11.4 A Simple Integer Processor with 251
Function Calls
11.5 An Averaging Filter 254
11.6 A Binary Coefficient-Weight FIR Filter 256
11.7 Retrospective 261
Chapter 11 Exercises 261
Chapter 12 A Simplified VHDL UART/COM Port 265
Receiver
12.1 Introduction 265
12.2 Receiver Architecture and Design 266
12.3 Receiver Simulation 273
12.4 Alternative Means of Instantiating 275
the Input Data Register
12.5 Retrospective 276
12.6 Appendix 12A: An Alternate VHDL 277
Receiver Source File
12.A An Alternate VHDL Receiver Source File 277
Chapter 12 Exercises 283
Chapter 13 VHDL and Digital Filter Design: 287
An Introduction
13.1 Introduction 287
13.2 Sampling of Continuous Signals 287
13.3 Frequency Content of Ideal Switching 291
Waveform
13.4 Frequency Content of the Sampled 292
Signal
13.5 Infinite and Finite Impulse Response 294
Systems
13.6 Finite Impulse Response Filters 295
13.7 A Simple FIR Filter Illustration 296
13.8 The Fourier-Series Method of FIR Design 298
13.8.1 A Rectangular Prototype for 300
Fourier Series Implementation
13.9 Retrospective 308
Chapter 13 Exercises 309
Index 311
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