Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Timing Analysis for Arrays
Last Edit July 22, 2001
Compute Lfo by adding the sum of the electrical loads of all loads driven. If a destination pin has a fan-in of 2, it counts as two electrical loads and as one physical pin. A destination may appear to have two physical loads internal to the macro. In these cases, the macro documentation will clearly identify the fan-in load represented by that pin. BiCMOS libraries have a higher average fan-in than do bipolar libraries.
Compute Lwo by multiplying the wire-OR load factor by the size of the wire-OR. For libraries that do not allow a wire-OR, this term becomes zero.
Example: For the AMCC Q5000, WIREOR4 = 1.2 loads.
For a non-RC tree, non-distributed estimate of metal delays, use the vendor-supplied equation to find the metal loading.
The cell sizes on the larger arrays in the same family are the same as for the smaller arrays. Since the distance from edge to edge of the array is larger, the average distance for an interconnect is larger. Therefore, the same macro path would be estimated as longer on the larger array than on the smaller one. Note that this is strictly the estimate - the actual delay will depend upon the macro positions and the actual routing paths.
where (net size - 1) is the physical pin count of the loads driven plus the number of sources on the net (assuming a wire-OR) minus one. When there is no wire-OR, (net size - 1) reduces to pins driven.
Q2000 Series a and b factors (Historical)
For the Q5000, b = 0.67 and a varies by array. The Q5000T uses a = 3.84 and the Q1300T uses a = 1.96. For a macro driving a net sized 8 (net size - 1 = 7), this converts to 14.14 load units for the Q5000T and 6.63 load units for the Q1300T.