Last Edit July 22, 2001
When I first wrote this book, I had spent a considerable amount of time
in the Bit-Slice and ASIC industry. The book reflected the design procedures
at that moment. It was a reflection of the class I taught at AMCC and
at UCSD for 11.5 years. From there I developed and taught the technical
training classes for CBA (cell-based array) designs. Now, even CBA is
beginning to fade as standard cells take over a the dominant array-based
As of January 2001, there have been some changes, although not as many
as people would like to think. The basic design flow? - It is still with
- The size of the designs has changed from what could be handled by
a human (up to 50,000 gates) to what must be handled by a computer (12
million gates). We are seeing designs that run 4-6 millions gates per
ASIC and will be seeing 10-12 million designs shortly.
- Wafers have gone from 3" to 6-8" and are headed for 12".
- From primarily bipolar, I now work almost exclusively with CMOS.
- The process technology has gone from 5 microns to 0.18 deep sub-micron,
and everything bipolar designers worried about is now the headache that
concerns CMOS designers - namely, that gate delays are practically negligible
compared to interconnect delays. DSM (deep sub-micron) refers to this
- By 1998, CBA ASICs still ruled, but by 2000 standard cells had become
dominant, producing smaller and faster designs.
- Libraries still exist but now macro selection is by a synthesis software
package and 85% of designs are done with the Synopsys Design Compiler
package. Cadence now has a competitive synthesis package.
- Schematic capture is pretty much an anachronism and design are specified
in Verilog or VHDL (RTL).
- Software tools take the design from RTL (register-transfer logic)
through wafer-verification, with software like Dracula, Vampire), performing
ATT (antenna checking), ERCs (electrical rules checking), DRCs (design
rule checking). Manual operations are no longer feasible.
- RAM and ROM onboard an ASIC is no longer unusual.
- IP (intellectual property) blocks are in common use. Design-Reuse
is a buzzword. IP may be multi-layered and fixed (hard IP), or soft
IP where a netlist is incorporated and the block may be altered by synthesis
- Vectors are generated by automatic test vector generation software.
- Designs are made DFT (design for test) as a routine step in the compile
process. DFT is no longer an option.
- Software can tell you if your design is testable and if it is routable.
- Place and Route are no longer a last step in the process. Floorplanners
are required for any sizable design. Cadence's Gate Ensemble and Silicon
Ensemble were the leaders in Place and Route. Synopsys has the Chip
Architect floorplanner. Cadence has the Logical and Physical design
planners. Avant! has Planit! for floorplanning tasks.
- Everybody's floorplanner has to talk to everybody's synthesis tool
and they both have to talk to everybody's place&route software.
Everybody has to talk to PrimeTime.
- What AMCC called "intermediate annotation" is what is produced
during floorplanning and it's use is not optional..
- EDIF became the standard for netlists. There is no more concern about
whose netlist went where. EDIF is used to input to floorplanners, and
EDIF is produced by the systhesis tools and by the place&route tool.
- DB has become a standard format.
- DEF (design exchange format - Cadence) became the standard for input
- PDEF 2.0 is the standard output of the floorplanners and is now standard
input to place&route software. PDEF 3.0 is on the horizon.
- SDF 2.0 is used for delay files and can be created by PrimeTime from
delay information from most floorplanners and place&route tools.
- SPICE files are still with us
- VCS, VSS and related tools perform simulation.
- GDSII is for building the basedie layers and GDSII is produced by
the place&route software
- PrimeTime is the standard for static timing analysis (85% of design
are verified with that software).
- Designers no longer have to "fit" their designs into a fixed-size
chip with a fixed I/O count (cells in the I/O ring). Dies are designed
to fit the design. Holes are punched through the layers to accommodate
IP blocks (Hard IP blocks) and software exists to "stitch"
the IP blocks into the basedie.
- You may not "diddle" with parametric specifications. If
you have a different set of operating conditions, you must go back to
the library vendor for new library specifications. The slightest variation
can have dire consequences in the results.
- The axiom that the engineer who knew the library could do better designs
than a more experienced engineer who did not, still holds. You may "direct"
the use of macros by the synthesis tools.
- Tcl has become the standard interface scripting language.
In fact, Synopsys alone has approximately 42 different software tools
available to help create an ASIC design. Design flow from RTL to wafer
fab is the focus of most vendors today.