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Mentor Graphics Announces Complete Design through Manufacturing Solution in TSMC Reference Flow 10.0

WILSONVILLE, Ore. — (BUSINESS WIRE) — July 23, 2009 Mentor Graphics Corporation (NASDAQ: MENT) today announced that it has expanded the set of Mentor tools and technologies included in TSMC Reference Flow 10.0. The expanded Mentor® track supports advanced functional verification for complex ICs, netlist-to-GDSII implementation for 28nm ICs, tighter integration with the ubiquitous Calibre® physical verification and DFM platform, and tools for layout aware test failure diagnosis. In addition, this newly introduced Mentor track also addresses low power design with Mentor tools for functional verification, IC implementation and IC testing.

“Mentor Graphics continues to expand its Reference Flow offerings to cover the total IC design cycle from the systems level through functional verification, place-and-route, physical verification and silicon test, as well as offering new solutions such as low power, manufacturing variability, and silicon yield analysis,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

The Reference Flow 10.0 Mentor track provides new capabilities in many areas, including the first Mentor implementation solution in TSMC Reference Flow, the Olympus-SoC™ place-and-route system. For advanced IC implementation, the Olympus-SoC system has new features addressing on-chip variation, 28nm routing and low power design:

Design-for-Manufacturing capabilities within the Olympus-SoC and Calibre platforms have been expanded and more tightly integrated to address manufacturing variability issues at 28nm and beyond:

In addition, the Calibre nmDRC and Calibre nmLVS products support signoff physical verification of 2D and 3D system in package (SIP) designs in Reference Flow 10.0.

Reference Flow 10.0 includes new features in the TestKompress® and YieldAssist™ products for better fault detection, power-aware testing and failure diagnosis:

Reference Flow 10.0 also includes advanced functional verification features from the Questa® and 0-In® platforms for improved validation of complex IC designs.

“The complete Mentor design-to-silicon track in TSMC’s Reference Flow 10.0 allows us to address our mutual customers’ biggest challenges for 28nm, including low power design and verification, large-scale SoC implementation, manufacturing variability, and cost-effective test and yield analysis,” said Walden C. Rhines, chairman and CEO, Mentor Graphics. “The industry transition to 28nm processes also presents new technical challenges, which Mentor is in a unique position to solve. Our close collaboration with TSMC allows us to close the loop between designers and foundries with tools that help our customers get their products to market faster with higher performance and greater reliability.”

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics, Mentor, 0-In, Calibre, Eldo, Questa and TestKompress are registered trademarks and LFD, Olympus-SoC, xRC and YieldAssist are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)


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