A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter

7.1. Introduction

Low-power techniques at the highest level of abstraction as architectural level and algorithmic level can lead to power savings which cannot be obtained unless the complete system is taken into study. This chapter presents a 16-bit D/A interface with Sinc approximated semidigital reconstruction filter as an example of a system where accuracy and noise give constraints on the power consumption of the system [1], [2]. As we will see, reducing power in the analog domain the power in the digital domain is also reduced.

Practical D/A interfaces suffer from circuit nonidealities such as component noise, mismatches, device nonlinearities, substrate bounce and clock jitter which can impair the resolution of the complete system [3], [4], [5], [6], [7]. Because of those imperfections, the analog reconstruction is the most difficult analog building block in a DSP system. In a switched capacitor D/A the exponential charge transfer is inherently nonlinear generating too much distortion [8], [9], [10]. Besides we need two opamps for charge summing and low-pass filtering. In this respect, a current driven D/A it is a better choice [11]. This chapter presents a differential, current-driven 16-bit D/A interface with Sinc approximated semidigital reconstruction filter.

An important problem to be discussed in the chapter is the optimization of the number of coefficients. An FIR filter with a large number of coefficients needs a large number of additional digital circuitry increasing the area, power consumption and complicating more the clock distribution. A large number of coefficients, requires more shift registers and therefore, the power in digital domain will increase. Moreover, the accuracy of the coefficients is subject to process tolerance caused by rounding of the small coefficients and quantization to the process grid span [11]. A large number of coefficients implies big differences between coefficients. The accuracy of the smaller coefficients is impaired with consequences on the stop-band rejection.

By using Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of out of band noise. A differential solution is proposed to reduce the digital crosstalk and to increase the output signal swing. An analysis of the matching, noise and clock jitter is provided. The D/A interface has been realized on chip in a 0.8mm CMOS 5V technology and the measurement results are presented.

Another approach is the Sinc approximation method in the time domain. By using this method, power can be shifted from the digital domain into analog domain and the best partitioning of the system in terms of power can be found. The price paid is an increase of the filter complexity with the benefit of keeping the same power consumption in the analog part. The principle of the method is discussed and an example is given.