Power considerations in sub-micron digital CMOS
To optimize the power dissipation of mixed level systems a low-power methodology should be applied throughout the design process from system-level to process-level while keeping the same performance of the system. Low-power design methodologies can be considered at several abstraction levels as system, algorithmic ,architectural, logical and physical (device/process) as illustrated in fig.2.1. The process technology is under the control of process and device engineers. The other levels can be controlled by the design engineer.
Fig.2.1: The levels of abstraction for power considerations
Low-power techniques at the highest level of abstraction as algorithmic and architectural can lead to power savings of several orders of magnitude. At this level of abstraction, power analysis allows an early prediction and optimization of the power of a system.
Starting from fundamental/physical limits we are discussing afterwards the practical limits of power in digital, mostly at the architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. At architecture level, it is possible to find relations between power and signal to noise which provide a comparison basis with analog solutions. Because the computational power of an algorithm implemented in one chip solution dominates, we have made some considerations regarding the computational power. A simple example of a digital filter shows how power can be saved at the architecture level. Last but not least, ways to low-power in digital are being discussed. They will provide some input for the analog part of this thesis.