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15.11  References

Page numbers in brackets after the reference indicate the location in the chapter body.

Cheng, C.-K., and Y.-C. A. Wei. 1991. “An improved two-way partitioning algorithm with stable performance.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, no. 12, pp. 1502–1511. Describes the ratio-cut algorithm. [ reference location ]

Fiduccia, C. M., and R. M. Mattheyses. 1982. “A linear-time heuristic for improving network partitions.” In Proceedings of the 19th Design Automation Conference, pp. 175–181. Describes modification to Kernighan-Lin algorithm to reduce computation time. [ reference location ]

Gajski, D. D., N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin. 1992. High-Level Synthesis: Introduction to Chip and System Design. Norwell, MA: Kluwer. ISBN 0-7923-9194-2. TK7874.H52422. Chapter 6, Partitioning, is an introduction to system-level partitioning algorithms. It also includes a description of the system partitioning features of SpecSyn, a research tool developed at UC-Irvine. [ reference location ]

Goto, S., and T. Matsud. 1986. “Partitioning, assignment and placement.” In Layout Design and Verification. Vol. 4 of Advances in CAD for VLSI (T. Ohtsuki, Ed.) pp. 55–97, New York: Elsevier. [ reference location ]

Kernighan, B. W., and S. Lin. 1970. “An efficient heuristic procedure for partitioning graphs.” Bell Systems Technical Journal, Vol. 49, no. 2, February, pp. 291–307. The original description of the Kernighan–Lin partitioning algorithm. [ reference location ]

Kirkpatrick, S., et al. 1983. “Optimization by simulated annealing.” Science, Vol. 220, no. 4598, pp. 671–680. [ reference location ]

Kucukcakar, K., and A. C. Parker, 1991. “CHOP: A constraint-driven system-level partitioner.” In Proceedings of the 28th Design Automation Conference, pp. 514–519. [ reference location ]

Lagnese, E., and D. Thomas. 1991. “Architectural partitioning for system level synthesis of integrated circuits.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, no. 7, pp. 847–860. [ reference location ]

Najm, F. N. 1994. “A survey of power estimation techniques in VLSI circuits.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, no. 4, pp. 446–455. 43 refs. [ reference location ]

Preas, B. T., and P. G. Karger, 1988. “Placement, assignment and floorplanning.” In Physical Design Automation of VLSI Systems (B. T. Preas and M. J. Lorenzetti, Eds.), pp. 87–155. Menlo Park, CA: Benjamin-Cummings. ISBN 0-8053-0412-9. TK7874.P47. [ reference location ]

Rose, J., W. Klebsch, and J. Wolf, 1990. “Temperature measurement and equilibrium dynamics of simulated annealing placements.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, no. 3, pp. 253–259. Discusses ways to speed up simulated annealing. [ reference location ]

Schweikert, D. G., and B. W. Kernighan. 1979. “A proper model for the partitioning of electrical circuits.” In Proceedings of the 9th Design Automation Workshop. Points out the difference between nets and edges. [ reference location , reference location ]

Sechen, C. 1988. VLSI Placement and Global Routing Using Simulated Annealing. New York: Kluwer. Introduction; The Simulated Annealing Algorithm; Placement and Global Routing of Standard Cell Integrated Circuits; Macro/Custom Cell Chip-Planning, Placement, and Global Routing; Average Interconnection Length Estimation; Interconnect-Area Estimation for Macro Cell Placements; An Edge-Based Channel Definition Algorithm for Rectilinear Cells; A Graph-Based Global Router Algorithm; Conclusion; Island-Style Gate Array Placement. [ reference location ]

Sedgewick, R. 1988. Algorithms. Reading, MA: Addison-Wesley. ISBN 0-201-06673-4. QA76.6.S435. Reference for basic sorting and graph-searching algorithms. [ reference location ]

Sherwani, N. A. 1993. Algorithms for VLSI Physical Design Automation. Norwell, MA: Kluwer. ISBN 0-7923-9294-9. TK874.S455. [ reference location ]

Smailagic, A., et al. 1995. “Benchmarking an interdisciplinary concurrent design methodology for electronic/mechanical systems.” In Proceedings of the 32nd Design Automation Conference. San Francisco. Describes the evolution of the VuMan wearable computer. Includes some interesting measures of the complexity of system design. [ reference location ]

Veendrick, H. J. M. 1984. “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits.” IEEE Journal of Solid-State Circuits, Vol. SC-19, no. 4, pp. 468–473. [ reference location , reference location ]

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