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13.5  Cell Models

There are several different kinds of logic cell models:

  • Primitive models , which are produced by the ASIC library company and describe the function and properties of each logic cell (NAND, D flip-flop, and so on) using primitive functions.
  • Verilog and VHDL models that are produced by an ASIC library company from the primitive models.
  • Proprietary models produced by library companies that describe either small logic cells or larger functions such as microprocessors.

A logic cell model is different from the cell delay model, which is used to calculate the delay of the logic cell, from the power model , which is used to calculate power dissipation of the logic cell, and from the interconnect timing model , which is used to calculate the delays between logic cells (we return to these in Section 13.6 ).

13.5.1  Primitive Models

The following is an example of a primitive model from an ASIC library company (Compass Design Automation). This particular model (for a two-input NAND cell) is complex because it is intended for a 0.35 m m process and has some advanced delay modeling features. The contents are not important to an ASIC designer, but almost all of the information about a logic cell is derived from the primitive model. The designer does not normally see this primitive model; it may only be used by an ASIC library company to generate other models—Verilog or VHDL, for example.


(timingModel = oneOf("ism","pr"); powerModel = oneOf("pin"); )


Logic = Function (A1; A2; )Rec ZN = not (A1 AND A2); End; End;

miscInfo = Rec Title = "2-Input NAND, 1X Drive"; freq_fact = 0.5;

tml = "nd02d1 nand 2 * zn a1 a2";

MaxParallel = 1; Transistors = 4; power = 0.179018;

Width = 4.2; Height = 12.6; productName = "stdcell35"; libraryName = "cb35sc"; End;

Pin = Rec

A1 = Rec input; cap = 0.010; doc = "Data Input"; End;

A2 = Rec input; cap = 0.010; doc = "Data Input"; End;

ZN = Rec output; cap = 0.009; doc = "Data Output"; End; End;

Symbol = Select


On pr Do Rec

tA1D_fr = |( Rec prop = 0.078; ramp = 2.749; End);

tA1D_rf = |( Rec prop = 0.047; ramp = 2.506; End);

tA2D_fr = |( Rec prop = 0.063; ramp = 2.750; End);

tA2D_rf = |( Rec prop = 0.052; ramp = 2.507; End); End

On ism Do Rec

tA1D_fr = |( Rec A0 = 0.0015; dA = 0.0789; D0 = -0.2828;

dD = 4.6642; B = 0.6879; Z = 0.5630; End );

tA1D_rf = |( Rec A0 = 0.0185; dA = 0.0477; D0 = -0.1380;

dD = 4.0678; B = 0.5329; Z = 0.3785; End );

tA2D_fr = |( Rec A0 = 0.0079; dA = 0.0462; D0 = -0.2819;

dD = 4.6646; B = 0.6856; Z = 0.5282; End );

tA2D_rf = |( Rec A0 = 0.0060; dA = 0.0464; D0 = -0.1408;

dD = 4.0731; B = 0.6152; Z = 0.4064; End ); End; End;

Delay = |( Rec from = pin.A1; to = pin.ZN;

edges = Rec fr = Symbol.tA1D_fr; rf = Symbol.tA1D_rf; End; End, Rec from = pin.A2; to = pin.ZN; edges = Rec fr = Symbol.tA2D_fr; rf = Symbol.tA2D_rf; End; End );

MaxRampTime = |( Rec check = pin.A1; riseTime = 3.000; fallTime = 3.000; End, Rec check = pin.A2; riseTime = 3.000; fallTime = 3.000; End, Rec check = pin.ZN; riseTime = 3.000; fallTime = 3.000; End );

DynamicPower = |( Rec rise = { ZN }; val = 0.003; End); End; End

This primitive model contains the following information:

  • The logic cell name, the logic cell function expressed using primitive functions, and port names.
  • A list of supported delay models ( ism stands for input-slope delay model, and pr for prop–ramp delay model—see Section 13.6 ).
  • Miscellaneous data on the logic cell size, the number of transistors and so on—primarily for use by logic-synthesis tools and for data book generation.
  • Information for power dissipation models and timing analysis.

13.5.2 Synopsys Models

The ASIC library company may provide vendor models in formats unique to each CAD tool company. The following is an example of a Synopsys model derived from a primitive model similar to the example in Section 13.5.1 . In a Synopsys library, each logic cell is part of a large file that also contains wire-load models and other characterization information for the cell library.

cell (nd02d1) {

/* title : 2-Input NAND, 1X Drive */

/* pmd checksum : 'HBA7EB26C */

area : 1;

pin(a1) { direction : input; capacitance : 0.088;

fanout_load : 0.088; }

pin(a2) { direction : input; capacitance : 0.087;

fanout_load : 0.087; }

pin(zn) { direction : output; max_fanout : 1.786;

max_transition : 3; function : "(a1 a2)'";

timing() {

timing_sense : "negative_unate"

intrinsic_rise : 0.24 intrinsic_fall : 0.17

rise_resistance : 1.68 fall_resistance : 1.13

related_pin : "a1" }

timing() { timing_sense : "negative_unate"

intrinsic_rise : 0.32 intrinsic_fall : 0.18

rise_resistance : 1.68 fall_resistance : 1.13

related_pin : "a2"

} } } /* end of cell */

This file contains the only information the Synopsys logic synthesizer, simulator, and other design tools use. If the information is not in this model, the tools cannot produce it. You can see that not all of the information from a primitive model is necessarily present in a vendor model.

13.5.3  Verilog Models

The following is a Verilog model for an inverter (derived from a primitive model):





`timescale 1 ns / 1 ps

module in01d1 (zn, i); input i; output zn; not G2(zn, i);

specify specparam

InCap3 = 0.060, OutCap = 0.038, MaxLoad = 1.538,

R_Ramp3 = 0.542:0.980:1.750, F_Ramp3 = 0.605:1.092:1.950;

specparam cell_count = 1.000000; specparam Transistors = 4 ;

specparam Power = 1.400000; specparam MaxLoadedRamp = 3 ;

(i => zn) = (0.031:0.056:0.100, 0.028:0.050:0.090);






This is very similar in form to the model for the MUX of Section 13.2.1 , except that this model includes additional timing parameters (at the beginning of the specify block). These timing parameters were omitted to simplify the model of Section 13.2.1 (see Section 13.6 for an explanation of their function).

There are no standards on writing Verilog logic cell models. In the Verilog model, in01d1 , fixed delays (corresponding to zero load capacitance) are embedded in a specify block. The parameters describing the delay equations for the timing model and other logic cell parameters (area, power-model parameters, and so on) are specified using the Verilog specparam feature. Writing the model in this way allows the model information to be accessed using the Verilog PLI routines. It also allows us to back-annotate timing information by overriding the data in the specify block.

The following Verilog code tests the model for logic cell in01d1 :

`timescale 1 ns / 1 ps

module SDF_b; reg A; in01d1 i1 (B, A);

initial begin A = 0; #5; A = 1; #5; A = 0; end

initial ("T=%6g",," A=",A," B=",B);


T= 0 A=0 B=x

T= 0.056 A=0 B=1

T= 5 A=1 B=1

T= 5.05 A=1 B=0

T= 10 A=0 B=0

T=10.056 A=0 B=1

In this case the simulator has used the fixed, typical timing delays (0.056 ns for the rising delay, and 0.05 ns for the falling delay—both from line 12 in module in01d1 ). Here is an example SDF file (filename SDF_b.sdf ) containing back-annotation timing delays:


(SDFVERSION "3.0") (DESIGN "SDF.v") (DATE "Aug-13-96")



(CELL (CELLTYPE "in01d1")



(IOPATH i zn (1.151:1.151:1.151) (1.363:1.363:1.363))




(Notice that since Verilog is case sensitive, the instance names and node names in the SDF file are also case sensitive.) This SDF file describes the path delay between input (pin i ) and output (pin zn ) as 1.151 ns (rising delay—minimum, typical, and maximum are identical in this simple example) and 1.363 ns (falling delay). These delays are calculated by a delay calculator . The delay calculator may be a stand-alone tool or part of the simulator. This tool calculates the delay values by using the delay parameters in the logic cell model (lines 8 9 in module in01d1 ).

We call a system task, , to perform back-annotation,

`timescale 1 ns / 1 ps

module SDF_b; reg A; in01d1 i1 (B, A);

initial begin

( "SDF_b.sdf", SDF_b, , "sdf_b.log", "minimum", , );

A = 0; #5; A = 1; #5; A = 0; end

initial ("T=%6g",," A=",A," B=",B);


Here is the output (from MTI V-System/Plus) including back-annotated timing:

T= 0 A=0 B=x

T= 1.151 A=0 B=1

T= 5 A=1 B=1

T= 6.363 A=1 B=0

T= 10 A=0 B=0

T=11.151 A=0 B=1

The delay information from the SDF file has been passed to the simulator.

Back-annotation is not part of the IEEE 1364 Verilog standard, although many Verilog-compatible simulators do support the system task. Many ASIC vendors require the use of Verilog to complete a back-annotated timing simulation before they will accept a design for manufacture. Used in this way Verilog is referred to as a golden simulator , since an ASIC vendor uses Verilog to judge whether an ASIC design fabricated using its process will work.

13.5.4 VHDL Models

Initially VHDL did not offer a standard way to perform back-annotation. Here is an example of a VHDL model for an inverter used to perform a back-annotated timing simulation using an Altera programmable ASIC:

library IEEE; use IEEE.STD_LOGIC_1164. all ;


entity bknot is

generic (derating : REAL := 1.0; Z1_cap : REAL := 0.000;


port (Z2 : in Std_Logic; Z1 : out STD_LOGIC);

end bknot;

architecture bknot of bknot is

constant tplh_Z2_Z1 : TIME := (1.00 ns + (0.01 ns * Z1_Cap)) * derating;

constant tphl_Z2_Z1 : TIME := (1.00 ns + (0.01 ns * Z1_Cap)) * derating;


process (Z2)

variable int_Z1 : Std_Logic := 'U';

variable tplh_Z1, tphl_Z1, Z1_delay : time := 0 ns;



int_Z1 := not (Z2);

if Z2'EVENT then

tplh_Z1 := tplh_Z2_Z1; tphl_Z1 := tphl_Z2_Z1;

end if ;

Z1_delay := F_Delay(int_Z1, tplh_Z1, tphl_Z1);

Z1 <= int_Z1 after Z1_delay;

end process ;

end bknot;

configuration bknot_CON of bknot is for bknot end for ;

end bknot_CON;

This model accepts two generic parameters: load capacitance, Z1_cap , and a derating factor, derating , used to adjust postlayout timing delays. The proliferation of different VHDL back-annotation techniques drove the VHDL community to develop a standard method to complete back-annotation—VITAL.

13.5.5  VITAL Models

VITAL is the VHDL Initiative Toward ASIC Libraries, IEEE Std 1076.4 [ 1995]. 1 VITAL allows the use of sign-off quality ASIC libraries with VHDL simulators. Sign-off is the transfer of a design from a customer to an ASIC vendor. If the customer has completed simulation of a design using sign-off quality models from an approved cell library and a golden simulator, the customer and ASIC vendor will sign off the design (by signing a contract) and the vendor guarantees that the silicon will match the simulation.

VITAL models, like Verilog models, may be generated from primitive models. Here is an example of a VITAL-compliant model for an inverter,

library IEEE; use IEEE.STD_LOGIC_1164. all ;

use IEEE.VITAL_timing. all ; use IEEE.VITAL_primitives. all ;

entity IN01D1 is

generic (

tipd_I : VitalDelayType01 := (0 ns, 0 ns);

tpd_I_ZN : VitalDelayType01 := (0 ns, 0 ns) );

port (

I : in STD_LOGIC := 'U';

ZN : out STD_LOGIC := 'U' );

attribute VITAL_LEVEL0 of IN01D1 : entity is TRUE;

end IN01D1;

architecture IN01D1 of IN01D1 is

attribute VITAL_LEVEL1 of IN01D1 : architecture is TRUE;

signal I_ipd : STD_LOGIC := 'X';



begin VitalWireDelay(I_ipd, I, tipd_I); end block ;

VITALbehavior : process (I_ipd)

variable ZN_zd : STD_LOGIC;

variable ZN_GlitchData : VitalGlitchDataType;


ZN_zd := VitalINV(I_ipd);


OutSignal => ZN,

OutSignalName => "ZN",

OutTemp => ZN_zd,

Paths => (0 => (I_ipd'LAST_EVENT, tpd_I_ZN, TRUE)),

GlitchData => ZN_GlitchData,

DefaultDelay => VitalZeroDelay01,

Mode => OnEvent,

MsgOn => FALSE,

XOn => TRUE,

MsgSeverity => ERROR);

end process ;

end IN01D1;

The following testbench, SDF_testbench , contains an entity, SDF , that in turn instantiates a copy of an inverter, in01d1 :

library IEEE; use IEEE.STD_LOGIC_1164. all ;

entity SDF is port ( A : in STD_LOGIC; B : out STD_LOGIC );

end SDF;

architecture SDF of SDF is

component in01d1 port ( I : in STD_LOGIC; ZN : out STD_LOGIC );

end component ;

begin i1: in01d1 port map ( I => A, ZN => B);

end SDF;

library STD; use STD.TEXTIO. all ;

library IEEE; use IEEE.STD_LOGIC_1164. all ;

entity SDF_testbench is end SDF_testbench;

architecture SDF_testbench of SDF_testbench is

component SDF port ( A : in STD_LOGIC; B : out STD_LOGIC );

end component ;

signal A, B : STD_LOGIC := '0';


SDF_b : SDF port map ( A => A, B => B);

process begin

A <= '0'; wait for 5 ns; A <= '1';

wait for 5 ns; A <= '0'; wait ;

end process ;

process (A, B) variable L: LINE; begin

write(L, now, right, 10, TIME'(ps));

write(L, STRING'(" A=")); write(L, TO_BIT(A));

write(L, STRING'(" B=")); write(L, TO_BIT(B));

writeline(output, L);

end process ;

end SDF_testbench;

Here is an SDF file ( SDF_b.sdf ) that contains back-annotation timing information (min/typ/max timing values are identical in this example):


(SDFVERSION "3.0") (DESIGN "SDF.vhd") (DATE "Aug-13-96")



(CELL (CELLTYPE "in01d1")



(IOPATH i zn (1.151:1.151:1.151) (1.363:1.363:1.363))

(PORT i (0.021:0.021:0.021) (0.025:0.025:0.025))




(VHDL is case insensitive, but to allow the use of an SDF file with both Verilog and VHDL we must maintain case.) As in the Verilog example in Section 13.5.3 the logic cell delay (from the input pin of the inverter, i , to the output pin, zn ) follows the IOPATH keyword. In this example there is also an interconnect delay that follows the PORT keyword. The interconnect delay has been placed, or lumped, at the input of the inverter. In order to include back-annotation timing using the SDF file, SDF_b.sdf , we use a command-line switch to the simulator. In the case of MTI V-System/Plus the command is as follows:

<msmith/MTI/vital> vsim -c -sdfmax /sdf_b=SDF_b.sdf sdf_testbench


# 0 ps A=0 B=0

# 0 ps A=0 B=0

# 1176 ps A=0 B=1

# 5000 ps A=1 B=1

# 6384 ps A=1 B=0

# 10000 ps A=0 B=0

# 11176 ps A=0 B=1

We have to explain to the simulator where in the design hierarchy to apply the timing information in the SDF file. The situation is like giving someone directions “Go North on the M1 and turn left at the third intersection,” but where do we start? London or Birmingham? VHDL needs much more precise directions. Using VITAL we say we back-annotate to a region . The switch /sdf_b=SDF_b.sdf specifies that all instance names in the SDF file, SDF_b.sdf , are relative to the region /sdf_b . The region refers to instance name sdf_b (line 9 in entity SDF_testbench ), which is an instance of component SDF . Component SDF in turn contains an instance of a component, in01d1 , with instance name i1 (line 7 in architecture SDF ). Through this rather (for us) difficult-to-follow set of directions, the simulator knows that

... (CELL (CELLTYPE "in01d1") (INSTANCE i1) ...

refers to (SDF) cell or (VHDL) component in01d1 with instance name i1 in instance SDF_b of the compiled model sdf_testbench .

Notice that we cannot use an SDF file of the following form (as we did for the Verilog version of this example):

... (CELL (CELLTYPE "in01d1") (INSTANCE SDF_b.i1) ...

There is no instance in the VHDL model “higher” than instance name SDF_b that we can use as a starting point for VITAL back-annotation. In the Verilog SDF file we can refer to the name of the top-level module ( SDF_b in line 2 in module SDF_b ). We cannot do this in VHDL; we must name an instance. The result is that, unless you are careful in constructing the hierarchy of your VHDL design, you may not be able to use the same SDF file for back-annotating both VHDL and Verilog.

13.5.6  SDF in Simulation

SDF was developed to handle back-annotation, but it is also used to describe forward-annotation of timing constraints from logic synthesis. Here is an example of an SDF file that contains the timing information for the halfgate ASIC design:



(DESIGN "halfgate_ASIC_u")

(DATE "Aug-13-96")

(VENDOR "Compass")


(VERSION "v9r1.2")



(CELL (CELLTYPE "in01d0")

(INSTANCE v_1.B1_i1)


(IOPATH I ZN (1.151:1.151:1.151) (1.363:1.363:1.363))



(CELL (CELLTYPE "pc5o06")



(IOPATH I PAD (1.216:1.216:1.216) (1.249:1.249:1.249))



(CELL (CELLTYPE "pc5d01r")



(IOPATH PAD CIN (.169:.169:.169) (.199:.199:.199))




This SDF file describes the delay due to the input pad (cell pc5d01r , instance name u0_2 ), our inverter (cell in01d0 , instance name v_1.B1_i1 ), and the output pad (cell pc5o06 , instance name u1_2 ). Since this SDF file was produced before any physical layout, there are no estimates for interconnect delay. The following partial SDF file illustrates how interconnect delay can be specified in SDF.




(TEMPERATURE 0:55:100)





( INTERCONNECT A.INV8.OUT B.DFF1.Q (:0.6:) (:0.6:))


This SDF file specifies an interconnect delay (using the keyword INTERCONNECT ) of 60 ps (0.6 units with a timescale of 100 ps per unit) between the output port of an inverter with instance name A.INV8 (note that '.' is the hierarchy divider) in block A and the Q input port of a D flip-flop (instance name B.DFF1 ) in block B.

The triplet notation (min : typ : max) in SDF corresponds to minimum, typical, and maximum values of a parameter. Specifying two triplets corresponds to rising (the first triplet) and falling delays. A single triplet corresponds to both. A third triplet corresponds to turn-off delay (transitions to or from 'Z' ). You can also specify six triplets (rising, falling, '0' to 'Z' , 'Z' to '1' , '1' to 'Z' , and 'Z' to '0' ). When only the typical value is specified, the minimum and maximum are set equal to the typical value.

Logic cell delays can use several models in SDF. Here is one example:



( IOPATH (POSEDGE CLK) Q (12:14:15) (11:13:15))))

The IOPATH construct specifies a delay between the input pin and the output pin of a cell. In this example the delay is between the positive edge of the clock (input port) and the flip-flop output.

The following example SDF file is for an AO221 logic cell:



(DATE "26 AUG 1996")



(VERSION "3.0")


(VOLTAGE 3.6:3.3:3.0)

(PROCESS "-3.0:0.0:3.0")

(TEMPERATURE 0.0:25.0:115.0)






(IOPATH A1 Y (1.11:1.42:2.47) (1.39:1.78:3.19))

(IOPATH A2 Y (0.97:1.30:2.34) (1.53:1.94:3.50))

(IOPATH B1 Y (1.26:1.59:2.72) (1.52:2.01:3.79))

(IOPATH B2 Y (1.10:1.45:2.56) (1.66:2.18:4.10))

(IOPATH C1 Y (0.79:1.04:1.91) (1.36:1.62:2.61))


1. IEEE Std 1076.4-1995, © 1995 IEEE. All rights reserved.

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