One way to learn more about logic synthesis is to obtain a copy of misII or sis (or their newest derivatives) from the University of California at Berkeley (UCB). These tools form the basis of most commercially available logic-synthesis software. Included with the sis distribution is a PostScript copy of a tutorial paper (available also as ERL Memorandum UCB/ERL M92/41) on logic synthesis by the UCB synthesis group. The internal help in sis explains the theory and purpose of each command. In addition each logic-synthesis step is available separately so it is possible to see the logic being synthesized, optimized, and mapped.
Programmable ASIC vendors, Xilinx, Altera, and Actel have each produced reports explaining how to use Synopsys, Mentor, Cadence, and other synthesis tools with their products. These are available on these companies’ Web sites.
Brayton [ 1984] describes the detailed operation of espresso , one of the first logic-minimization programs, and the foundation of most modern commercial logic-synthesis tools. Edited books by Birtwistle and Subrahmanyam  and Dutton [ 1991] contain a collection of papers on logic synthesis. The book by Thomas et al.  describes an early logic-synthesis system. A tutorial paper by Brayton, Hachtel, and Sangiovanni-Vincentelli [ 1990] is an advanced description of multilevel logic optimization. In this chapter we have focused on RTL synthesis; the edited books by Camposano and Wolf ; Walker and Camposano ; and Michel, Lauther, and Duzy  contain papers on higher-level, or behavioral-level synthesis. Edwards provides an overview of synthesis including references to earlier work [ 1992]. Gebotys and Elmasry  cover system-level synthesis. Sasao [ 1993] is a selection of papers from a conference on logic synthesis. Kurup and Abbasi [ 1995] describe the Synopsys logic-synthesis tools. The book by Murgai et al. [ 1995] focuses on logic synthesis for FPGAs. De Micheli’s book  is a detailed work on logic-synthesis algorithms. Ashar et al. [ 1992] and Lavagno and Sangiovanni-Vincentelli  cover sequential logic synthesis in their books. The book by Airiau, Berge, and Olive  covers VHDL-93 from the perspective of logic synthesis. A book by Knapp , describing the Synopsys behavioral compiler, is the closest to this book’s treatment of logic synthesis, and includes several practical examples.
I have included references for a number of books (some not yet published) that I was unable to obtain before this book went to press including titles by Rushton  on logic synthesis using VHDL; Saucier  on architectural synthesis; Hachtel and Somenzi  on verification; Romdhane, Madisetti, and Hines  on behavioral synthesis; and Villa et al.  on FSM synthesis. I have included as much information as possible for these references including the LOC catalog information (it is possible to obtain an ISBN before publication).