10.1 A Counter
The following VHDL model describes an electrical "black box" that contains a 50 MHz clock generator and a counter. The counter increments on the negative edge of the clock, counting from zero to seven, and then begins at zero again. The model contains separate processes that execute at the same time as each other. Modeling concurrent execution is the major difference between HDLs and computer programming languages such as C.
entity Counter_1 is end; -- declare a "black box" called Counter_1 library STD; use STD.TEXTIO.all; -- we need this library to print architecture Behave_1 of Counter_1 is -- describe the "black box" -- declare a signal for the clock, type BIT, initial value '0' signal Clock : BIT := '0'; -- declare a signal for the count, type INTEGER, initial value 0 signal Count : INTEGER := 0; begin process begin -- process to generate the clock wait for 10 ns; -- a delay of 10 ns is half the clock cycle Clock <= not Clock; if (now > 340 ns) then wait; end if; -- stop after 340 ns end process; -- process to do the counting, runs concurrently with other processes process begin -- wait here until the clock goes from 1 to 0 wait until (Clock = '0'); -- now handle the counting if (Count = 7) then Count <= 0; else Count <= Count + 1; end if; end process; process (Count) variable L: LINE; begin -- process to print write(L, now); write(L, STRING'(" Count=")); write(L, Count); writeline(output, L); end process; end;
Throughout this book VHDL keywords (reserved words that are part of the language) are shown in bold type in code examples (but not in the text). The code examples use the bold keywords to improve readability. VHDL code is often lengthy and the code in this book is always complete wherever possible. In order to save space many of the code examples do not use the conventional spacing and formatting that is normally considered good practice. So "Do as I say and not as I do."
> vlib work > vcom Counter_1.vhd Model Technology VCOM V-System VHDL/Verilog 4.5b -- Loading package standard -- Compiling entity counter_1 -- Loading package textio -- Compiling architecture behave_1 of counter_1 > vsim -c counter_1 # Loading /../std.standard # Loading /../std.textio(body) # Loading work.counter_1(behave_1) VSIM 1> run 500 # 0 ns Count=0 # 20 ns Count=1 (...15 lines omitted...) # 340 ns Count=1 VSIM 2> quit >