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7.2 Xilinx LCA
Figure 7.5 shows the hierarchical Xilinx LCA interconnect architecture.
 The vertical lines and horizontal lines run between CLBs.
 The generalpurpose interconnect joins switch boxes (also known as magic boxes or switching matrices).
 The long lines run across the entire chip. It is possible to form internal buses using long lines and the threestate buffers that are next to each CLB.
 The direct connections (not used on the XC4000) bypass the switch matrices and directly connect adjacent CLBs.
 The Programmable Interconnection Points ( PIP s) are programmable pass transistors that connect the CLB inputs and outputs to the routing network.
 The bidirectional ( BIDI ) interconnect buffers restore the logic level and logic strength on long interconnect paths.
Table 7.3 shows the interconnect data for an XC3020, a typical Xilinx LCA FPGA, that uses twolevel metal interconnect. Figure 7.6 shows the switching matrix. Programming a switch matrix allows a number of different connections between the generalpurpose interconnect.
In Figure 7.6 (d), (g), and (h):
 C1 = 3CP1 + 3CP2 + 0. 5C _{ LX} is the parasitic capacitance due to the switch matrix and PIPs (F4, C4, G4) for CLB1, and half of the line capacitance for the doublelength line adjacent to CLB1.
 C _{ P1} and R _{ P1} are the switchingmatrix parasitic capacitance and resistance.
 C _{ P2} and R _{ P2} are the parasitic capacitance and resistance for the PIP connecting YQ of CLB1 and F4 of CLB3.
 C2 = 0. 5CLX + CLX accounts for half of the line adjacent to CLB1 and the line adjacent to CLB2.
 C _{ 3} = 0. 5C _{ LX } accounts for half of the line adjacent to CLB3.
 C _{ 4} = 0. 5C _{ LX} + 3C _{ P2} + C _{ LX} + 3C _{ P1} accounts for half of the line adjacent to CLB3, the PIPs of CLB3 (C4, G4, YQ), and the rest of the line and switch matrix capacitance following CLB3.
We can determine Elmore’s time constant for the connection shown in Figure 7.6 as
R_{ P2} (C_{ P2} + C_{ 2} + 3C_{ P1} ) + (R_{ P2} + R_{ P1} )(3C_{ P1} + C_{ 3} + C_{ P2} ) 

If RP1 = RP2 , and CP1 = CP2 , then
We need to know the passtransistor resistance RP . For example, suppose RP = 1k W . If k^{ '} _{ n} = 50 m AV^{ –2} , then (with Vt n = 0.65 V and V _{ DD} = 3.3 V)
If L = 1 m m, both source and drain areas are 7.5 m m long and approximately 3 m m wide (determined by diffusion overlap of contact, contact width, and contacttogate spacing, rules 6.1a + 6.2a + 6.4a = 5.5 l in Table 2.7 ). Both drain and source areas are thus 23 m m^{ 2} and the sidewall perimeters are 14 m m (excluding the sidewall facing the channel). If we have a diffusion capacitance of 140 aF m m^{ –2} (area) and 500 aF m m^{ –1} (perimeter), typical values for a 1.0 m m process, the parasitic source and drain capacitance is
If we assume CP = 0.01 pF and CLX = 0.075 pF ( Table 7.3 ),
A delay of approximately 1 ns agrees with the typical values from the XACT delay calculator and is about the fastest connection we can make between two CLBs.
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