- a. Build a spreadsheet, “Break-even Analysis,” to generate Figure 1.11.
- b. Derive equations for the break-even volumes (there are three: FPGA/MGA, FPGA/CBIC, and MGA/CBIC) and calculate their values.
- c. Increase the FPGA part cost by $10 and use your spreadsheet to produce the new break-even graph. Hint: (For users of Excel-like spreadsheets) use the XY scatter plot option. Use the first column for the x -axis data.
- d. Find the new break-even volumes (change the volume until the cost becomes the same for two technologies).
- e. Program your spreadsheet to automatically find the break-even volumes. Now graph the break-even volume (for a choice between FPGA and CBIC) for values of FPGA part costs ranging from $10–$50 and CBIC costs ranging from $2–$10 (do not change the fixed costs from Figure 1.12).
- f. Calculate the sensitivity of the break-even volumes to changes in the part costs and fixed costs. There are three break-even volumes and each of these is sensitive to two part costs and two fixed costs. Express your answers in two ways: in equation form and as numbers (for the values in Section 1.4.2 and Figure 1.11).
- g. The costs in Figure 1.11 are not unrealistic. What can you say from your answers if you are a defense contractor, primarily selling products in volumes of less than 1000 parts? What if you are a PC board vendor selling between 10,000 and 100,000 parts?
1.2 (Design productivity, 10 min.) Given the figures for the SPARCstation 1 ASICs described in Section 1.3 what was the productivity measured in transistors/day? and measured in gates/day? Compare your answers with the figures for productivity in Section 1.4.3 and explain any differences. How accurate do you think productivity estimates are?
1.3 (ASIC package size, 30 min.) Assuming, for this problem, a gate density of 1.0 gate/mil 2 (see Section 15.4, “Estimating ASIC Size,” for a detailed explanation of this figure), the maximum number of gates you can put in a package is determined by the maximum die size for each of the packages shown in Table 1.4. The maximum die size is determined by the package cavity size; these are package-limited ASICs. Calculate the maximum number of I/O pads that can be placed on a die for each package if the pad spacing is: (i) 5 mil, and (ii) 10 mil. Compare your answers with the maximum numbers of pins (or leads) on each package and comment. Now calculate the minimum number of gates that you can put in each package determined by the minimum die size.
Maximum die size 2 (mil 2 )
Minimum die size 3 (mil 2 )
1.4 (ASIC vendor costs, 30 min.) There is a well-known saying in the ASIC business: “We lose money on every part—but we make it up in volume.” This has a serious side. Suppose Sumo Silicon currently has two customers: Mr. Big, who currently buys 10,000 parts per week, and Ms. Smart, who currently buys 4800 parts per week. A new customer, Ms. Teeny (who is growing fast), wants to buy 1200 parts per week. Sumo’s costs are
Currently Sumo has a profit margin of 35 percent. Sumo is currently running at 100 wafer starts per week for Mr. Big and Ms. Smart. Sumo thinks they can get 50 cents more out of Mr. Big for his chips, but Ms. Smart won’t pay any more. We can calculate how much Sumo can afford to lose per chip if they want Ms. Teeny’s business really badly.
- a. What is Sumo’s current yield?
- b. How many good parts is Sumo currently producing per week? ( Hint: Is this enough to supply Mr. Big and Ms. Smart?)
- c. Calculate how many extra wafer starts per week we need to supply Ms. Teeny (the yield will change—what is the new yield?). Think when you give this answer.
- d. What is Sumo’s increase in costs to supply Ms. Teeny?
- e. Multiply your answer to part d by 1.35 (to account for Sumo’s profit). This is the increase in revenue we need to cover our increased costs to supply Ms. Teeny.
- f. Now suppose we charge Mr. Big 50 cents more per part. How much extra revenue does that generate?
- g. How much does Ms. Teeny’s extra business reduce the wafer cost?
- h. How much can Sumo Silicon afford to lose on each of Ms. Teeny’s parts, cover its costs, and still make a 35 percent profit?
1.5 (Silicon, 20 min.) How much does a 6-inch silicon wafer weigh? a 12-inch wafer? How much does a carrier (called a boat) that holds twenty 12-inch wafers weigh? What implications does this have for manufacturing?
- a. How many die that are 1-inch on a side does a 12-inch wafer hold? If each die is worth $100, how much is a 20-wafer boat worth? If a factory is processing 10 of these boats in different furnaces when the power is interrupted and those wafers have to be scrapped, how much money is lost?
- b. The size of silicon factories (fabs or foundries) is measured in wafer starts per week. If a factory is capable of 5000 12-inch wafer starts per week, with an average die of 500 mil on a side that sells for $20 and 90 percent yield, what is the value in dollars/year of the factory production? What fraction of the current gross national (or domestic) product (GNP/GDP) of your country is that? If the yield suddenly drops from 90 percent to 40 percent (a yield bust) how much revenue is the company losing per day? If the company has a cash reserve of $100 million and this revenue loss drops “straight to the bottom line,” how long does it take for the company to go out of business?
- c. TSMC produced 2 million 6-inch wafers in 1996, how many 500 mil die is that? TSMC’s $500 million Camas fab in Washington is scheduled to produce 30,000 8-inch wafers per month by the year 2000 using a 0.35 mm process. If a 1 Mb SRAM yields 1500 good die per 8-inch wafer and there are 1700 gross die per wafer, what is the yield? What is the die size? If the SRAM cell size is 7 mm 2 , what fraction of the die is used by the cells? What is TSMC’s cost per bit for SRAM if the wafer cost is $2000? If a 16Mb DRAM on the same fab line uses a 16 mm 2 die, what is the cost per bit for DRAM assuming the same yield?
1.6 (Simulation time, 30 min.) “. . . The system-level simulation used approximately 4000 lines of SPARC assembly language . . . each simulation clock was simulated in three real time seconds” (Sun Technology article).
- a. With a 20 MHz clock how much slower is simulated time than real time?
- b. How long would it take to simulate all 4000 lines of test code? (Assume one line of assembly code per cycle—a good approximation compared to the others we are making.)
The article continues: “the entire system was simulated, running actual code, including several milliseconds of SunOS execution. Four days after power-up, SPARCstation 1 booted SunOS and announced: 'hello world' .”
- c. How long would it take to simulate 5 ms of code?
- d. Find out how long it takes to boot a UNIX workstation in real time. How many clock cycles is this?
- e. The machine is not executing boot code all this time; you have to wait for disk drives to spin-up, file systems checks to complete, and so on. Make some estimates as to how much code is required to boot an operating system (OS) and how many clock cycles this would take to execute.
- f. From your answers make an estimate of how long it takes to simulate booting the OS. Does this seem reasonable?
- g. Could the engineers have simulated a complete boot sequence?
- h. Do you think the engineers expected the system to boot on first silicon, given the complexity of the system and how long they would have to wait to simulate a complete boot sequence? Explain.
1.7 (Price per gate, 5 min.) Given the assumptions of Section 1.4.4 on the price per gate of different ASIC technologies, what has to change for the price per gate for an FPGA to be less than that for an MGA or CBIC—if all three use the same process?
1.8 (Pentiums, 20 min.) Read the online tour of the Pentium Pro at http://www.intel.com (adapted from a paper presented at the 1995 International Solid-State Circuits Conference). This is not an ASIC design; notice the section on full-custom circuit design. Notice also the comments on the use of 'assert' statements in the HDL code that described the circuits. Find out the approximate cost of the Intel Pentium (3.3 million transistors) and Pentium Pro (5.5 million transistors) microprocessors.
- a. Assuming there a four transistors per gate equivalent, what is the price per gate?
- b. Find out the cost of a 1 Mb, 4 Mb, 8 Mb, or 16 Mb DRAM. Assuming one transistor per memory bit, what is the price per gate of DRAM?
- c. Considering that both have roughly the same die size, are just as complex to design and to manufacture, why is there such a huge difference in price per gate between microprocessors and DRAM?
1.9 (Inverse embedded arrays, 10 min.) A relatively new cousin of the embedded gate array, the inverse-embedded gate array , is a cell-based ASIC that contains an embedded gate-array megacell. List the features as well as the advantages and disadvantages of this type of ASIC in the same way as for the other members of the ASIC family in Section 1.1.
1.10 (0.5-gate design, 60 min.) It is a good idea to complete a 0.5-gate ASIC design (an inverter connected between an input pad and an output pad) in the first week (day) of class. Capture the commands in a report that shows all the steps taken to create your chip starting from an empty directory— halfgate .